| commit | 2ef444f1600bfc2d8522df0f537aafef79befa7e | [log] [tgz] |
|---|---|---|
| author | Chao Peng <chao.p.peng@linux.intel.com> | Wed Oct 24 16:05:12 2018 +0800 |
| committer | Paolo Bonzini <pbonzini@redhat.com> | Fri Dec 21 11:28:35 2018 +0100 |
| tree | 1bdc097495a69ed493a21ef07cb07e77db0da902 | |
| parent | 86f5201df0d3e3efc78d3eac7fc5a59b813287cd [diff] |
KVM: x86: Add Intel PT context switch for each vcpu Load/Store Intel Processor Trace register in context switch. MSR IA32_RTIT_CTL is loaded/stored automatically from VMCS. In Host-Guest mode, we need load/resore PT MSRs only when PT is enabled in guest. Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>