| commit | 2c0408dd0d8906b26fe8023889af7adf5e68b2c2 | [log] [tgz] |
|---|---|---|
| author | Alexander Shiyan <shc_work@mail.ru> | Thu Dec 20 11:06:38 2018 +0300 |
| committer | Philipp Zabel <p.zabel@pengutronix.de> | Thu Jan 17 14:58:55 2019 +0100 |
| tree | 6dfd05bb395da7b3ac66bba0c479a1a2b686e6bd | |
| parent | 4fb873c9648e383206e0a91cef9b03aa54066aca [diff] |
gpu: ipu-v3: Fix i.MX51 CSI control registers offset
The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative
to the control module registers on IPUv3EX.
This patch fixes wrong values for i.MX51 CSI0/CSI1.
Fixes: 2ffd48f2e7 ("gpu: ipu-v3: Add Camera Sensor Interface unit")
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>