| commit | 26e5378d115501a7cab25fdfc6ab10ccb5e4106f | [log] [tgz] |
|---|---|---|
| author | José Roberto de Souza <jose.souza@intel.com> | Wed Mar 28 15:30:44 2018 -0700 |
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | Fri Mar 30 10:18:09 2018 -0700 |
| tree | cf5ee73c071e92ce413e73ca497ae51cb606b6b0 | |
| parent | fe36181be371f3d98441cc23ccbfa89783fa55b1 [diff] |
drm/i915/psr: Cache sink synchronization latency This value do not change overtime so better cache it than fetch it every PSR enable. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180328223046.16125-8-jose.souza@intel.com