tree cbe66da90fef8dbe77435dbfe4b6b7ab4c2f4298
parent 43262f001b318a0c0531e252b47bc6b07794f356
author Saheed O. Bolarinwa <refactormyself@gmail.com> 1637350650 +0100
committer Bjorn Helgaas <bhelgaas@google.com> 1637361969 -0600

PCI/ASPM: Stop caching link L0s, L1 exit latencies

Previously we calculated the upstream and downstream L0s and L1 exit
latencies of the link in pcie_aspm_cap_init() and cached them in struct
pcie_link_state.latency_*.

These values are only used in pcie_aspm_check_latency() where they are
compared with the acceptable latencies on the link.  This path is used when
removing or changing the D state of the device, so it's relatively low
frequency.

To reduce the amount of per-link data we store, remove the latency_*
entries from struct pcie_link_state and calculate the latencies directly
where they are needed.

Link: https://lore.kernel.org/r/20211119193732.12343-3-refactormyself@gmail.com
Signed-off-by: Saheed O. Bolarinwa <refactormyself@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>