| commit | 21eb1850fa0bd0a9b729bf3708da78888433027f | [log] [tgz] |
|---|---|---|
| author | Chris Wilson <chris@chris-wilson.co.uk> | Wed Aug 01 11:47:21 2018 +0100 |
| committer | Chris Wilson <chris@chris-wilson.co.uk> | Wed Aug 01 14:13:06 2018 +0100 |
| tree | 97500f8e4fcda8b5917c67ec11933fc84e37f897 | |
| parent | 60548c554be2830d29d2533dad0ac8133347ee51 [diff] [blame] |
drm/i95: Mark GGTT as incoherent for gen10+ The evidence suggests that we need to start treating writes via GGTT as incoherent for gen10+, that is that they are internally buffered and not immediately visible via a read along a different physical path. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107398 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107400 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107435 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180801104721.4030-1-chris@chris-wilson.co.uk
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index e443fe4..adf8056 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -590,6 +590,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = { GEN9_FEATURES, \ GEN(10), \ .ddb_size = 1024, \ + .has_coherent_ggtt = false, \ GLK_COLORS static const struct intel_device_info intel_cannonlake_info = {