Merge branches 'clk-spreadtrum', 'clk-mvebu-dvfs', 'clk-qoriq', 'clk-imx' and 'clk-qcom-ipq8074' into clk-next
* clk-spreadtrum:
clk: sprd: add clocks support for SC9860
clk: sprd: Add dt-bindings include file for SC9860
dt-bindings: Add Spreadtrum clock binding documentation
clk: sprd: add adjustable pll support
clk: sprd: add composite clock support
clk: sprd: add divider clock support
clk: sprd: add mux clock support
clk: sprd: add gate clock support
clk: sprd: Add common infrastructure
clk: move clock common macros out from vendor directories
* clk-mvebu-dvfs:
clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks
clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFS
clk: mvebu: armada-37xx-periph: cosmetic changes
* clk-qoriq:
clk: qoriq: add more divider clocks support
* clk-imx:
clk: imx51: uart4, uart5 gates only exist on imx50, imx53
* clk-qcom-ipq8074:
clk: qcom: ipq8074: add misc resets for PCIE and NSS
dt-bindings: clock: qcom: add misc resets for PCIE and NSS
clk: qcom: ipq8074: add GP and Crypto clocks
clk: qcom: ipq8074: add NSS ethernet port clocks
clk: qcom: ipq8074: add NSS clocks
clk: qcom: ipq8074: add PCIE, USB and SDCC clocks
clk: qcom: ipq8074: add remaining PLL’s
dt-bindings: clock: qcom: add remaining clocks for IPQ8074
clk: qcom: ipq8074: fix missing GPLL0 divider width
clk: qcom: add parent map for regmap mux
clk: qcom: add read-only divider operations
diff --git a/Documentation/devicetree/bindings/clock/hi3660-clock.txt b/Documentation/devicetree/bindings/clock/hi3660-clock.txt
index 0035a7e..946da7c 100644
--- a/Documentation/devicetree/bindings/clock/hi3660-clock.txt
+++ b/Documentation/devicetree/bindings/clock/hi3660-clock.txt
@@ -13,12 +13,18 @@
- "hisilicon,hi3660-pmuctrl"
- "hisilicon,hi3660-sctrl"
- "hisilicon,hi3660-iomcu"
+ - "hisilicon,hi3660-stub-clk"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
+Optional Properties:
+
+- mboxes: Phandle to the mailbox for sending message to MCU.
+ (See: ../mailbox/hisilicon,hi3660-mailbox.txt for more info)
+
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
diff --git a/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt b/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt
new file mode 100644
index 0000000..7474aba
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,spmi-clkdiv.txt
@@ -0,0 +1,59 @@
+Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
+
+clkdiv configures the clock frequency of a set of outputs on the PMIC.
+These clocks are typically wired through alternate functions on
+gpio pins.
+
+=======================
+Properties
+=======================
+
+- compatible
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,spmi-clkdiv".
+
+- reg
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: base address of CLKDIV peripherals.
+
+- qcom,num-clkdivs
+ Usage: required
+ Value type: <u32>
+ Definition: number of CLKDIV peripherals.
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: reference to the xo clock.
+
+- clock-names:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "xo".
+
+- #clock-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: shall contain 1.
+
+=======
+Example
+=======
+
+pm8998_clk_divs: clock-controller@5b00 {
+ compatible = "qcom,spmi-clkdiv";
+ reg = <0x5b00>;
+ #clock-cells = <1>;
+ qcom,num-clkdivs = <3>;
+ clocks = <&xo_board>;
+ clock-names = "xo";
+
+ assigned-clocks = <&pm8998_clk_divs 1>,
+ <&pm8998_clk_divs 2>,
+ <&pm8998_clk_divs 3>;
+ assigned-clock-rates = <9600000>,
+ <9600000>,
+ <9600000>;
+};
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index 6498e1f..97f46ad 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -78,6 +78,7 @@
2 hwaccel index (n in CLKCGnHWACSR)
3 fman 0 for fm1, 1 for fm2
4 platform pll 0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+ 4=pll/5, 5=pll/6, 6=pll/7, 7=pll/8
5 coreclk must be 0
3. Example
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index b0ea753..3a1812f 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -41,7 +41,7 @@ struct clockgen_pll_div {
};
struct clockgen_pll {
- struct clockgen_pll_div div[4];
+ struct clockgen_pll_div div[8];
};
#define CLKSEL_VALID 1
@@ -1127,6 +1127,13 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
struct clk *clk;
int ret;
+ /*
+ * For platform PLL, there are 8 divider clocks.
+ * For core PLL, there are 4 divider clocks at most.
+ */
+ if (idx != PLATFORM_PLL && i >= 4)
+ break;
+
snprintf(pll->div[i].name, sizeof(pll->div[i].name),
"cg-pll%d-div%d", idx, i + 1);
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 96c6b6b..da44f8d 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -1424,7 +1424,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
base = of_iomap(np, 0);
if (!base) {
- pr_err("%s: unable to map resource", np->name);
+ pr_err("%s: unable to map resource\n", np->name);
return;
}
diff --git a/drivers/clk/clk-stm32h7.c b/drivers/clk/clk-stm32h7.c
index 61c3e40..db2b162 100644
--- a/drivers/clk/clk-stm32h7.c
+++ b/drivers/clk/clk-stm32h7.c
@@ -1,20 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) Gabriel Fernandez 2017
- * Author: Gabriel Fernandez <gabriel.fernandez@st.com>
- *
- * License terms: GPL V2.0.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
+ * Copyright (C) STMicroelectronics 2017
+ * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
*/
#include <linux/clk.h>
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 647d056..3526bc0 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -62,6 +62,7 @@ struct clk_core {
bool orphan;
unsigned int enable_count;
unsigned int prepare_count;
+ unsigned int protect_count;
unsigned long min_rate;
unsigned long max_rate;
unsigned long accuracy;
@@ -86,6 +87,7 @@ struct clk {
const char *con_id;
unsigned long min_rate;
unsigned long max_rate;
+ unsigned int exclusive_count;
struct hlist_node clks_node;
};
@@ -170,6 +172,11 @@ static void clk_enable_unlock(unsigned long flags)
spin_unlock_irqrestore(&enable_lock, flags);
}
+static bool clk_core_rate_is_protected(struct clk_core *core)
+{
+ return core->protect_count;
+}
+
static bool clk_core_is_prepared(struct clk_core *core)
{
bool ret = false;
@@ -381,6 +388,11 @@ bool clk_hw_is_prepared(const struct clk_hw *hw)
return clk_core_is_prepared(hw->core);
}
+bool clk_hw_rate_is_protected(const struct clk_hw *hw)
+{
+ return clk_core_rate_is_protected(hw->core);
+}
+
bool clk_hw_is_enabled(const struct clk_hw *hw)
{
return clk_core_is_enabled(hw->core);
@@ -519,6 +531,139 @@ EXPORT_SYMBOL_GPL(__clk_mux_determine_rate_closest);
/*** clk api ***/
+static void clk_core_rate_unprotect(struct clk_core *core)
+{
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return;
+
+ if (WARN_ON(core->protect_count == 0))
+ return;
+
+ if (--core->protect_count > 0)
+ return;
+
+ clk_core_rate_unprotect(core->parent);
+}
+
+static int clk_core_rate_nuke_protect(struct clk_core *core)
+{
+ int ret;
+
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return -EINVAL;
+
+ if (core->protect_count == 0)
+ return 0;
+
+ ret = core->protect_count;
+ core->protect_count = 1;
+ clk_core_rate_unprotect(core);
+
+ return ret;
+}
+
+/**
+ * clk_rate_exclusive_put - release exclusivity over clock rate control
+ * @clk: the clk over which the exclusivity is released
+ *
+ * clk_rate_exclusive_put() completes a critical section during which a clock
+ * consumer cannot tolerate any other consumer making any operation on the
+ * clock which could result in a rate change or rate glitch. Exclusive clocks
+ * cannot have their rate changed, either directly or indirectly due to changes
+ * further up the parent chain of clocks. As a result, clocks up parent chain
+ * also get under exclusive control of the calling consumer.
+ *
+ * If exlusivity is claimed more than once on clock, even by the same consumer,
+ * the rate effectively gets locked as exclusivity can't be preempted.
+ *
+ * Calls to clk_rate_exclusive_put() must be balanced with calls to
+ * clk_rate_exclusive_get(). Calls to this function may sleep, and do not return
+ * error status.
+ */
+void clk_rate_exclusive_put(struct clk *clk)
+{
+ if (!clk)
+ return;
+
+ clk_prepare_lock();
+
+ /*
+ * if there is something wrong with this consumer protect count, stop
+ * here before messing with the provider
+ */
+ if (WARN_ON(clk->exclusive_count <= 0))
+ goto out;
+
+ clk_core_rate_unprotect(clk->core);
+ clk->exclusive_count--;
+out:
+ clk_prepare_unlock();
+}
+EXPORT_SYMBOL_GPL(clk_rate_exclusive_put);
+
+static void clk_core_rate_protect(struct clk_core *core)
+{
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return;
+
+ if (core->protect_count == 0)
+ clk_core_rate_protect(core->parent);
+
+ core->protect_count++;
+}
+
+static void clk_core_rate_restore_protect(struct clk_core *core, int count)
+{
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return;
+
+ if (count == 0)
+ return;
+
+ clk_core_rate_protect(core);
+ core->protect_count = count;
+}
+
+/**
+ * clk_rate_exclusive_get - get exclusivity over the clk rate control
+ * @clk: the clk over which the exclusity of rate control is requested
+ *
+ * clk_rate_exlusive_get() begins a critical section during which a clock
+ * consumer cannot tolerate any other consumer making any operation on the
+ * clock which could result in a rate change or rate glitch. Exclusive clocks
+ * cannot have their rate changed, either directly or indirectly due to changes
+ * further up the parent chain of clocks. As a result, clocks up parent chain
+ * also get under exclusive control of the calling consumer.
+ *
+ * If exlusivity is claimed more than once on clock, even by the same consumer,
+ * the rate effectively gets locked as exclusivity can't be preempted.
+ *
+ * Calls to clk_rate_exclusive_get() should be balanced with calls to
+ * clk_rate_exclusive_put(). Calls to this function may sleep.
+ * Returns 0 on success, -EERROR otherwise
+ */
+int clk_rate_exclusive_get(struct clk *clk)
+{
+ if (!clk)
+ return 0;
+
+ clk_prepare_lock();
+ clk_core_rate_protect(clk->core);
+ clk->exclusive_count++;
+ clk_prepare_unlock();
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(clk_rate_exclusive_get);
+
static void clk_core_unprepare(struct clk_core *core)
{
lockdep_assert_held(&prepare_lock);
@@ -905,10 +1050,9 @@ static int clk_disable_unused(void)
}
late_initcall_sync(clk_disable_unused);
-static int clk_core_round_rate_nolock(struct clk_core *core,
- struct clk_rate_request *req)
+static int clk_core_determine_round_nolock(struct clk_core *core,
+ struct clk_rate_request *req)
{
- struct clk_core *parent;
long rate;
lockdep_assert_held(&prepare_lock);
@@ -916,6 +1060,38 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
if (!core)
return 0;
+ /*
+ * At this point, core protection will be disabled if
+ * - if the provider is not protected at all
+ * - if the calling consumer is the only one which has exclusivity
+ * over the provider
+ */
+ if (clk_core_rate_is_protected(core)) {
+ req->rate = core->rate;
+ } else if (core->ops->determine_rate) {
+ return core->ops->determine_rate(core->hw, req);
+ } else if (core->ops->round_rate) {
+ rate = core->ops->round_rate(core->hw, req->rate,
+ &req->best_parent_rate);
+ if (rate < 0)
+ return rate;
+
+ req->rate = rate;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void clk_core_init_rate_req(struct clk_core * const core,
+ struct clk_rate_request *req)
+{
+ struct clk_core *parent;
+
+ if (WARN_ON(!core || !req))
+ return;
+
parent = core->parent;
if (parent) {
req->best_parent_hw = parent->hw;
@@ -924,22 +1100,32 @@ static int clk_core_round_rate_nolock(struct clk_core *core,
req->best_parent_hw = NULL;
req->best_parent_rate = 0;
}
+}
- if (core->ops->determine_rate) {
- return core->ops->determine_rate(core->hw, req);
- } else if (core->ops->round_rate) {
- rate = core->ops->round_rate(core->hw, req->rate,
- &req->best_parent_rate);
- if (rate < 0)
- return rate;
+static bool clk_core_can_round(struct clk_core * const core)
+{
+ if (core->ops->determine_rate || core->ops->round_rate)
+ return true;
- req->rate = rate;
- } else if (core->flags & CLK_SET_RATE_PARENT) {
- return clk_core_round_rate_nolock(parent, req);
- } else {
- req->rate = core->rate;
- }
+ return false;
+}
+static int clk_core_round_rate_nolock(struct clk_core *core,
+ struct clk_rate_request *req)
+{
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return 0;
+
+ clk_core_init_rate_req(core, req);
+
+ if (clk_core_can_round(core))
+ return clk_core_determine_round_nolock(core, req);
+ else if (core->flags & CLK_SET_RATE_PARENT)
+ return clk_core_round_rate_nolock(core->parent, req);
+
+ req->rate = core->rate;
return 0;
}
@@ -996,10 +1182,17 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
clk_prepare_lock();
+ if (clk->exclusive_count)
+ clk_core_rate_unprotect(clk->core);
+
clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate);
req.rate = rate;
ret = clk_core_round_rate_nolock(clk->core, &req);
+
+ if (clk->exclusive_count)
+ clk_core_rate_protect(clk->core);
+
clk_prepare_unlock();
if (ret)
@@ -1432,34 +1625,23 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core,
clk_core_get_boundaries(core, &min_rate, &max_rate);
/* find the closest rate and parent clk/rate */
- if (core->ops->determine_rate) {
+ if (clk_core_can_round(core)) {
struct clk_rate_request req;
req.rate = rate;
req.min_rate = min_rate;
req.max_rate = max_rate;
- if (parent) {
- req.best_parent_hw = parent->hw;
- req.best_parent_rate = parent->rate;
- } else {
- req.best_parent_hw = NULL;
- req.best_parent_rate = 0;
- }
- ret = core->ops->determine_rate(core->hw, &req);
+ clk_core_init_rate_req(core, &req);
+
+ ret = clk_core_determine_round_nolock(core, &req);
if (ret < 0)
return NULL;
best_parent_rate = req.best_parent_rate;
new_rate = req.rate;
parent = req.best_parent_hw ? req.best_parent_hw->core : NULL;
- } else if (core->ops->round_rate) {
- ret = core->ops->round_rate(core->hw, rate,
- &best_parent_rate);
- if (ret < 0)
- return NULL;
- new_rate = ret;
if (new_rate < min_rate || new_rate > max_rate)
return NULL;
} else if (!parent || !(core->flags & CLK_SET_RATE_PARENT)) {
@@ -1564,6 +1746,9 @@ static void clk_change_rate(struct clk_core *core)
best_parent_rate = core->parent->rate;
}
+ if (clk_pm_runtime_get(core))
+ return;
+
if (core->flags & CLK_SET_RATE_UNGATE) {
unsigned long flags;
@@ -1634,27 +1819,62 @@ static void clk_change_rate(struct clk_core *core)
/* handle the new child who might not be in core->children yet */
if (core->new_child)
clk_change_rate(core->new_child);
+
+ clk_pm_runtime_put(core);
+}
+
+static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core,
+ unsigned long req_rate)
+{
+ int ret, cnt;
+ struct clk_rate_request req;
+
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return 0;
+
+ /* simulate what the rate would be if it could be freely set */
+ cnt = clk_core_rate_nuke_protect(core);
+ if (cnt < 0)
+ return cnt;
+
+ clk_core_get_boundaries(core, &req.min_rate, &req.max_rate);
+ req.rate = req_rate;
+
+ ret = clk_core_round_rate_nolock(core, &req);
+
+ /* restore the protection */
+ clk_core_rate_restore_protect(core, cnt);
+
+ return ret ? 0 : req.rate;
}
static int clk_core_set_rate_nolock(struct clk_core *core,
unsigned long req_rate)
{
struct clk_core *top, *fail_clk;
- unsigned long rate = req_rate;
+ unsigned long rate;
int ret = 0;
if (!core)
return 0;
+ rate = clk_core_req_round_rate_nolock(core, req_rate);
+
/* bail early if nothing to do */
if (rate == clk_core_get_rate_nolock(core))
return 0;
+ /* fail on a direct rate set of a protected provider */
+ if (clk_core_rate_is_protected(core))
+ return -EBUSY;
+
if ((core->flags & CLK_SET_RATE_GATE) && core->prepare_count)
return -EBUSY;
/* calculate new rates and get the topmost changed clock */
- top = clk_calc_new_rates(core, rate);
+ top = clk_calc_new_rates(core, req_rate);
if (!top)
return -EINVAL;
@@ -1713,8 +1933,14 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
/* prevent racing with updates to the clock topology */
clk_prepare_lock();
+ if (clk->exclusive_count)
+ clk_core_rate_unprotect(clk->core);
+
ret = clk_core_set_rate_nolock(clk->core, rate);
+ if (clk->exclusive_count)
+ clk_core_rate_protect(clk->core);
+
clk_prepare_unlock();
return ret;
@@ -1722,6 +1948,53 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
EXPORT_SYMBOL_GPL(clk_set_rate);
/**
+ * clk_set_rate_exclusive - specify a new rate get exclusive control
+ * @clk: the clk whose rate is being changed
+ * @rate: the new rate for clk
+ *
+ * This is a combination of clk_set_rate() and clk_rate_exclusive_get()
+ * within a critical section
+ *
+ * This can be used initially to ensure that at least 1 consumer is
+ * statisfied when several consumers are competing for exclusivity over the
+ * same clock provider.
+ *
+ * The exclusivity is not applied if setting the rate failed.
+ *
+ * Calls to clk_rate_exclusive_get() should be balanced with calls to
+ * clk_rate_exclusive_put().
+ *
+ * Returns 0 on success, -EERROR otherwise.
+ */
+int clk_set_rate_exclusive(struct clk *clk, unsigned long rate)
+{
+ int ret;
+
+ if (!clk)
+ return 0;
+
+ /* prevent racing with updates to the clock topology */
+ clk_prepare_lock();
+
+ /*
+ * The temporary protection removal is not here, on purpose
+ * This function is meant to be used instead of clk_rate_protect,
+ * so before the consumer code path protect the clock provider
+ */
+
+ ret = clk_core_set_rate_nolock(clk->core, rate);
+ if (!ret) {
+ clk_core_rate_protect(clk->core);
+ clk->exclusive_count++;
+ }
+
+ clk_prepare_unlock();
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate_exclusive);
+
+/**
* clk_set_rate_range - set a rate range for a clock source
* @clk: clock source
* @min: desired minimum clock rate in Hz, inclusive
@@ -1732,6 +2005,7 @@ EXPORT_SYMBOL_GPL(clk_set_rate);
int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
{
int ret = 0;
+ unsigned long old_min, old_max, rate;
if (!clk)
return 0;
@@ -1745,12 +2019,46 @@ int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
clk_prepare_lock();
- if (min != clk->min_rate || max != clk->max_rate) {
- clk->min_rate = min;
- clk->max_rate = max;
- ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate);
+ if (clk->exclusive_count)
+ clk_core_rate_unprotect(clk->core);
+
+ /* Save the current values in case we need to rollback the change */
+ old_min = clk->min_rate;
+ old_max = clk->max_rate;
+ clk->min_rate = min;
+ clk->max_rate = max;
+
+ rate = clk_core_get_rate_nolock(clk->core);
+ if (rate < min || rate > max) {
+ /*
+ * FIXME:
+ * We are in bit of trouble here, current rate is outside the
+ * the requested range. We are going try to request appropriate
+ * range boundary but there is a catch. It may fail for the
+ * usual reason (clock broken, clock protected, etc) but also
+ * because:
+ * - round_rate() was not favorable and fell on the wrong
+ * side of the boundary
+ * - the determine_rate() callback does not really check for
+ * this corner case when determining the rate
+ */
+
+ if (rate < min)
+ rate = min;
+ else
+ rate = max;
+
+ ret = clk_core_set_rate_nolock(clk->core, rate);
+ if (ret) {
+ /* rollback the changes */
+ clk->min_rate = old_min;
+ clk->max_rate = old_max;
+ }
}
+ if (clk->exclusive_count)
+ clk_core_rate_protect(clk->core);
+
clk_prepare_unlock();
return ret;
@@ -1871,32 +2179,31 @@ bool clk_has_parent(struct clk *clk, struct clk *parent)
}
EXPORT_SYMBOL_GPL(clk_has_parent);
-static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
+static int clk_core_set_parent_nolock(struct clk_core *core,
+ struct clk_core *parent)
{
int ret = 0;
int p_index = 0;
unsigned long p_rate = 0;
+ lockdep_assert_held(&prepare_lock);
+
if (!core)
return 0;
- /* prevent racing with updates to the clock topology */
- clk_prepare_lock();
-
if (core->parent == parent)
- goto out;
+ return 0;
/* verify ops for for multi-parent clks */
- if ((core->num_parents > 1) && (!core->ops->set_parent)) {
- ret = -ENOSYS;
- goto out;
- }
+ if (core->num_parents > 1 && !core->ops->set_parent)
+ return -EPERM;
/* check that we are allowed to re-parent if the clock is in use */
- if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count) {
- ret = -EBUSY;
- goto out;
- }
+ if ((core->flags & CLK_SET_PARENT_GATE) && core->prepare_count)
+ return -EBUSY;
+
+ if (clk_core_rate_is_protected(core))
+ return -EBUSY;
/* try finding the new parent index */
if (parent) {
@@ -1904,15 +2211,14 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
if (p_index < 0) {
pr_debug("%s: clk %s can not be parent of clk %s\n",
__func__, parent->name, core->name);
- ret = p_index;
- goto out;
+ return p_index;
}
p_rate = parent->rate;
}
ret = clk_pm_runtime_get(core);
if (ret)
- goto out;
+ return ret;
/* propagate PRE_RATE_CHANGE notifications */
ret = __clk_speculate_rates(core, p_rate);
@@ -1934,8 +2240,6 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
runtime_put:
clk_pm_runtime_put(core);
-out:
- clk_prepare_unlock();
return ret;
}
@@ -1959,13 +2263,50 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
*/
int clk_set_parent(struct clk *clk, struct clk *parent)
{
+ int ret;
+
if (!clk)
return 0;
- return clk_core_set_parent(clk->core, parent ? parent->core : NULL);
+ clk_prepare_lock();
+
+ if (clk->exclusive_count)
+ clk_core_rate_unprotect(clk->core);
+
+ ret = clk_core_set_parent_nolock(clk->core,
+ parent ? parent->core : NULL);
+
+ if (clk->exclusive_count)
+ clk_core_rate_protect(clk->core);
+
+ clk_prepare_unlock();
+
+ return ret;
}
EXPORT_SYMBOL_GPL(clk_set_parent);
+static int clk_core_set_phase_nolock(struct clk_core *core, int degrees)
+{
+ int ret = -EINVAL;
+
+ lockdep_assert_held(&prepare_lock);
+
+ if (!core)
+ return 0;
+
+ if (clk_core_rate_is_protected(core))
+ return -EBUSY;
+
+ trace_clk_set_phase(core, degrees);
+
+ if (core->ops->set_phase)
+ ret = core->ops->set_phase(core->hw, degrees);
+
+ trace_clk_set_phase_complete(core, degrees);
+
+ return ret;
+}
+
/**
* clk_set_phase - adjust the phase shift of a clock signal
* @clk: clock signal source
@@ -1988,7 +2329,7 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
*/
int clk_set_phase(struct clk *clk, int degrees)
{
- int ret = -EINVAL;
+ int ret;
if (!clk)
return 0;
@@ -2000,15 +2341,13 @@ int clk_set_phase(struct clk *clk, int degrees)
clk_prepare_lock();
- trace_clk_set_phase(clk->core, degrees);
+ if (clk->exclusive_count)
+ clk_core_rate_unprotect(clk->core);
- if (clk->core->ops->set_phase)
- ret = clk->core->ops->set_phase(clk->core->hw, degrees);
+ ret = clk_core_set_phase_nolock(clk->core, degrees);
- trace_clk_set_phase_complete(clk->core, degrees);
-
- if (!ret)
- clk->core->phase = degrees;
+ if (clk->exclusive_count)
+ clk_core_rate_protect(clk->core);
clk_prepare_unlock();
@@ -2096,11 +2435,12 @@ static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
if (!c)
return;
- seq_printf(s, "%*s%-*s %11d %12d %11lu %10lu %-3d\n",
+ seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %-3d\n",
level * 3 + 1, "",
30 - level * 3, c->name,
- c->enable_count, c->prepare_count, clk_core_get_rate(c),
- clk_core_get_accuracy(c), clk_core_get_phase(c));
+ c->enable_count, c->prepare_count, c->protect_count,
+ clk_core_get_rate(c), clk_core_get_accuracy(c),
+ clk_core_get_phase(c));
}
static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
@@ -2122,7 +2462,8 @@ static int clk_summary_show(struct seq_file *s, void *data)
struct clk_core *c;
struct hlist_head **lists = (struct hlist_head **)s->private;
- seq_puts(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
+ seq_puts(s, " enable prepare protect \n");
+ seq_puts(s, " clock count count count rate accuracy phase\n");
seq_puts(s, "----------------------------------------------------------------------------------------\n");
clk_prepare_lock();
@@ -2158,6 +2499,7 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
seq_printf(s, "\"%s\": { ", c->name);
seq_printf(s, "\"enable_count\": %d,", c->enable_count);
seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
+ seq_printf(s, "\"protect_count\": %d,", c->protect_count);
seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
seq_printf(s, "\"phase\": %d", clk_core_get_phase(c));
@@ -2288,6 +2630,11 @@ static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
if (!d)
goto err_out;
+ d = debugfs_create_u32("clk_protect_count", S_IRUGO, core->dentry,
+ (u32 *)&core->protect_count);
+ if (!d)
+ goto err_out;
+
d = debugfs_create_u32("clk_notifier_count", S_IRUGO, core->dentry,
(u32 *)&core->notifier_count);
if (!d)
@@ -2678,7 +3025,13 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
ret = -ENOMEM;
goto fail_name;
}
+
+ if (WARN_ON(!hw->init->ops)) {
+ ret = -EINVAL;
+ goto fail_ops;
+ }
core->ops = hw->init->ops;
+
if (dev && pm_runtime_enabled(dev))
core->dev = dev;
if (dev && dev->driver)
@@ -2740,6 +3093,7 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
kfree_const(core->parent_names[i]);
kfree(core->parent_names);
fail_parent_names:
+fail_ops:
kfree_const(core->name);
fail_name:
kfree(core);
@@ -2851,7 +3205,7 @@ void clk_unregister(struct clk *clk)
/* Reparent all children to the orphan list. */
hlist_for_each_entry_safe(child, t, &clk->core->children,
child_node)
- clk_core_set_parent(child, NULL);
+ clk_core_set_parent_nolock(child, NULL);
}
hlist_del_init(&clk->core->child_node);
@@ -2859,6 +3213,11 @@ void clk_unregister(struct clk *clk)
if (clk->core->prepare_count)
pr_warn("%s: unregistering prepared clock: %s\n",
__func__, clk->core->name);
+
+ if (clk->core->protect_count)
+ pr_warn("%s: unregistering protected clock: %s\n",
+ __func__, clk->core->name);
+
kref_put(&clk->core->ref, __clk_release);
unlock:
clk_prepare_unlock();
@@ -3017,6 +3376,18 @@ void __clk_put(struct clk *clk)
clk_prepare_lock();
+ /*
+ * Before calling clk_put, all calls to clk_rate_exclusive_get() from a
+ * given user should be balanced with calls to clk_rate_exclusive_put()
+ * and by that same consumer
+ */
+ if (WARN_ON(clk->exclusive_count)) {
+ /* We voiced our concern, let's sanitize the situation */
+ clk->core->protect_count -= (clk->exclusive_count - 1);
+ clk_core_rate_unprotect(clk->core);
+ clk->exclusive_count = 0;
+ }
+
hlist_del(&clk->clks_node);
if (clk->min_rate > clk->core->req_rate ||
clk->max_rate < clk->core->req_rate)
diff --git a/drivers/clk/h8300/clk-div.c b/drivers/clk/h8300/clk-div.c
index 4ae6244..d413ade 100644
--- a/drivers/clk/h8300/clk-div.c
+++ b/drivers/clk/h8300/clk-div.c
@@ -24,13 +24,13 @@ static void __init h8300_div_clk_setup(struct device_node *node)
num_parents = of_clk_get_parent_count(node);
if (!num_parents) {
- pr_err("%s: no parent found", clk_name);
+ pr_err("%s: no parent found\n", clk_name);
return;
}
divcr = of_iomap(node, 0);
if (divcr == NULL) {
- pr_err("%s: failed to map divide register", clk_name);
+ pr_err("%s: failed to map divide register\n", clk_name);
goto error;
}
offset = (unsigned long)divcr & 3;
diff --git a/drivers/clk/h8300/clk-h8s2678.c b/drivers/clk/h8300/clk-h8s2678.c
index fc24b0b..b68045d 100644
--- a/drivers/clk/h8300/clk-h8s2678.c
+++ b/drivers/clk/h8300/clk-h8s2678.c
@@ -93,7 +93,7 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
num_parents = of_clk_get_parent_count(node);
if (!num_parents) {
- pr_err("%s: no parent found", clk_name);
+ pr_err("%s: no parent found\n", clk_name);
return;
}
@@ -104,13 +104,13 @@ static void __init h8s2678_pll_clk_setup(struct device_node *node)
pll_clock->sckcr = of_iomap(node, 0);
if (pll_clock->sckcr == NULL) {
- pr_err("%s: failed to map divide register", clk_name);
+ pr_err("%s: failed to map divide register\n", clk_name);
goto free_clock;
}
pll_clock->pllcr = of_iomap(node, 1);
if (pll_clock->pllcr == NULL) {
- pr_err("%s: failed to map multiply register", clk_name);
+ pr_err("%s: failed to map multiply register\n", clk_name);
goto unmap_sckcr;
}
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index 7098bfd..1bd4355 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -49,3 +49,9 @@
default ARCH_HISI
help
Build the Hisilicon Hi6220 stub clock driver.
+
+config STUB_CLK_HI3660
+ bool "Hi3660 Stub Clock Driver"
+ depends on COMMON_CLK_HI3660 && MAILBOX
+ help
+ Build the Hisilicon Hi3660 stub clock driver.
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 0e55612..4806fc2 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -15,3 +15,4 @@
obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
obj-$(CONFIG_RESET_HISI) += reset.o
obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
+obj-$(CONFIG_STUB_CLK_HI3660) += clk-hi3660-stub.o
diff --git a/drivers/clk/hisilicon/clk-hi3660-stub.c b/drivers/clk/hisilicon/clk-hi3660-stub.c
new file mode 100644
index 0000000..9b6c72b
--- /dev/null
+++ b/drivers/clk/hisilicon/clk-hi3660-stub.c
@@ -0,0 +1,185 @@
+/*
+ * Hisilicon clock driver
+ *
+ * Copyright (c) 2013-2017 Hisilicon Limited.
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * Author: Kai Zhao <zhaokai1@hisilicon.com>
+ * Tao Wang <kevin.wangtao@hisilicon.com>
+ * Leo Yan <leo.yan@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/mailbox_client.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/hi3660-clock.h>
+
+#define HI3660_STUB_CLOCK_DATA (0x70)
+#define MHZ (1000 * 1000)
+
+#define DEFINE_CLK_STUB(_id, _cmd, _name) \
+ { \
+ .id = (_id), \
+ .cmd = (_cmd), \
+ .hw.init = &(struct clk_init_data) { \
+ .name = #_name, \
+ .ops = &hi3660_stub_clk_ops, \
+ .num_parents = 0, \
+ .flags = CLK_GET_RATE_NOCACHE, \
+ }, \
+ },
+
+#define to_stub_clk(_hw) container_of(_hw, struct hi3660_stub_clk, hw)
+
+struct hi3660_stub_clk_chan {
+ struct mbox_client cl;
+ struct mbox_chan *mbox;
+};
+
+struct hi3660_stub_clk {
+ unsigned int id;
+ struct clk_hw hw;
+ unsigned int cmd;
+ unsigned int msg[8];
+ unsigned int rate;
+};
+
+static void __iomem *freq_reg;
+static struct hi3660_stub_clk_chan stub_clk_chan;
+
+static unsigned long hi3660_stub_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct hi3660_stub_clk *stub_clk = to_stub_clk(hw);
+
+ /*
+ * LPM3 writes back the CPU frequency in shared SRAM so read
+ * back the frequency.
+ */
+ stub_clk->rate = readl(freq_reg + (stub_clk->id << 2)) * MHZ;
+ return stub_clk->rate;
+}
+
+static long hi3660_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ /*
+ * LPM3 handles rate rounding so just return whatever
+ * rate is requested.
+ */
+ return rate;
+}
+
+static int hi3660_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct hi3660_stub_clk *stub_clk = to_stub_clk(hw);
+
+ stub_clk->msg[0] = stub_clk->cmd;
+ stub_clk->msg[1] = rate / MHZ;
+
+ dev_dbg(stub_clk_chan.cl.dev, "set rate msg[0]=0x%x msg[1]=0x%x\n",
+ stub_clk->msg[0], stub_clk->msg[1]);
+
+ mbox_send_message(stub_clk_chan.mbox, stub_clk->msg);
+ mbox_client_txdone(stub_clk_chan.mbox, 0);
+
+ stub_clk->rate = rate;
+ return 0;
+}
+
+static const struct clk_ops hi3660_stub_clk_ops = {
+ .recalc_rate = hi3660_stub_clk_recalc_rate,
+ .round_rate = hi3660_stub_clk_round_rate,
+ .set_rate = hi3660_stub_clk_set_rate,
+};
+
+static struct hi3660_stub_clk hi3660_stub_clks[HI3660_CLK_STUB_NUM] = {
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER0, 0x0001030A, "cpu-cluster.0")
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_CLUSTER1, 0x0002030A, "cpu-cluster.1")
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_GPU, 0x0003030A, "clk-g3d")
+ DEFINE_CLK_STUB(HI3660_CLK_STUB_DDR, 0x00040309, "clk-ddrc")
+};
+
+static struct clk_hw *hi3660_stub_clk_hw_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ unsigned int idx = clkspec->args[0];
+
+ if (idx >= HI3660_CLK_STUB_NUM) {
+ pr_err("%s: invalid index %u\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &hi3660_stub_clks[idx].hw;
+}
+
+static int hi3660_stub_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ unsigned int i;
+ int ret;
+
+ /* Use mailbox client without blocking */
+ stub_clk_chan.cl.dev = dev;
+ stub_clk_chan.cl.tx_done = NULL;
+ stub_clk_chan.cl.tx_block = false;
+ stub_clk_chan.cl.knows_txdone = false;
+
+ /* Allocate mailbox channel */
+ stub_clk_chan.mbox = mbox_request_channel(&stub_clk_chan.cl, 0);
+ if (IS_ERR(stub_clk_chan.mbox))
+ return PTR_ERR(stub_clk_chan.mbox);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ freq_reg = devm_ioremap(dev, res->start, resource_size(res));
+ if (!freq_reg)
+ return -ENOMEM;
+
+ freq_reg += HI3660_STUB_CLOCK_DATA;
+
+ for (i = 0; i < HI3660_CLK_STUB_NUM; i++) {
+ ret = devm_clk_hw_register(&pdev->dev, &hi3660_stub_clks[i].hw);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(&pdev->dev, hi3660_stub_clk_hw_get,
+ hi3660_stub_clks);
+}
+
+static const struct of_device_id hi3660_stub_clk_of_match[] = {
+ { .compatible = "hisilicon,hi3660-stub-clk", },
+ {}
+};
+
+static struct platform_driver hi3660_stub_clk_driver = {
+ .probe = hi3660_stub_clk_probe,
+ .driver = {
+ .name = "hi3660-stub-clk",
+ .of_match_table = hi3660_stub_clk_of_match,
+ },
+};
+
+static int __init hi3660_stub_clk_init(void)
+{
+ return platform_driver_register(&hi3660_stub_clk_driver);
+}
+subsys_initcall(hi3660_stub_clk_init);
diff --git a/drivers/clk/imx/clk-imx51-imx53.c b/drivers/clk/imx/clk-imx51-imx53.c
index 7bcaf27..c864992e 100644
--- a/drivers/clk/imx/clk-imx51-imx53.c
+++ b/drivers/clk/imx/clk-imx51-imx53.c
@@ -257,10 +257,6 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
- clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
- clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
- clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
- clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24);
clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
@@ -361,6 +357,10 @@ static void __init mx50_clocks_init(struct device_node *np)
clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+ clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
+ clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
+ clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
+ clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
@@ -562,6 +562,10 @@ static void __init mx53_clocks_init(struct device_node *np)
clk[IMX5_CLK_IEEE1588_PRED] = imx_clk_divider("ieee1588_pred", "ieee1588_sel", MXC_CCM_CSCDR2, 6, 3);
clk[IMX5_CLK_IEEE1588_PODF] = imx_clk_divider("ieee1588_podf", "ieee1588_pred", MXC_CCM_CSCDR2, 0, 6);
clk[IMX5_CLK_IEEE1588_GATE] = imx_clk_gate2("ieee1588_serial_gate", "ieee1588_podf", MXC_CCM_CCGR7, 6);
+ clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
+ clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
+ clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
+ clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index cecb0fd..ee8637c 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -21,9 +21,11 @@
*/
#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
+#include <linux/regmap.h>
#include <linux/slab.h>
#define TBG_SEL 0x0
@@ -33,6 +35,26 @@
#define CLK_SEL 0x10
#define CLK_DIS 0x14
+#define LOAD_LEVEL_NR 4
+
+#define ARMADA_37XX_NB_L0L1 0x18
+#define ARMADA_37XX_NB_L2L3 0x1C
+#define ARMADA_37XX_NB_TBG_DIV_OFF 13
+#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
+#define ARMADA_37XX_NB_CLK_SEL_OFF 11
+#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
+#define ARMADA_37XX_NB_TBG_SEL_OFF 9
+#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
+#define ARMADA_37XX_NB_CONFIG_SHIFT 16
+#define ARMADA_37XX_NB_DYN_MOD 0x24
+#define ARMADA_37XX_NB_DFS_EN 31
+#define ARMADA_37XX_NB_CPU_LOAD 0x30
+#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
+#define ARMADA_37XX_DVFS_LOAD_0 0
+#define ARMADA_37XX_DVFS_LOAD_1 1
+#define ARMADA_37XX_DVFS_LOAD_2 2
+#define ARMADA_37XX_DVFS_LOAD_3 3
+
struct clk_periph_driver_data {
struct clk_hw_onecell_data *hw_data;
spinlock_t lock;
@@ -46,7 +68,18 @@ struct clk_double_div {
u8 shift2;
};
+struct clk_pm_cpu {
+ struct clk_hw hw;
+ void __iomem *reg_mux;
+ u8 shift_mux;
+ u32 mask_mux;
+ void __iomem *reg_div;
+ u8 shift_div;
+ struct regmap *nb_pm_base;
+};
+
#define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
+#define to_clk_pm_cpu(_hw) container_of(_hw, struct clk_pm_cpu, hw)
struct clk_periph_data {
const char *name;
@@ -55,6 +88,7 @@ struct clk_periph_data {
struct clk_hw *mux_hw;
struct clk_hw *rate_hw;
struct clk_hw *gate_hw;
+ struct clk_hw *muxrate_hw;
bool is_double_div;
};
@@ -79,7 +113,9 @@ static const struct clk_div_table clk_table2[] = {
{ .val = 1, .div = 4, },
{ .val = 0, .div = 0, }, /* last entry */
};
+
static const struct clk_ops clk_double_div_ops;
+static const struct clk_ops clk_pm_cpu_ops;
#define PERIPH_GATE(_name, _bit) \
struct clk_gate gate_##_name = { \
@@ -121,6 +157,18 @@ struct clk_divider rate_##_name = { \
} \
};
+#define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \
+struct clk_pm_cpu muxrate_##_name = { \
+ .reg_mux = (void *)TBG_SEL, \
+ .mask_mux = 3, \
+ .shift_mux = _shift1, \
+ .reg_div = (void *)_reg, \
+ .shift_div = _shift2, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_pm_cpu_ops, \
+ } \
+};
+
#define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\
static PERIPH_GATE(_name, _bit); \
static PERIPH_MUX(_name, _shift); \
@@ -135,10 +183,6 @@ static PERIPH_DIV(_name, _reg, _shift1, _table);
static PERIPH_GATE(_name, _bit); \
static PERIPH_DIV(_name, _reg, _shift, _table);
-#define PERIPH_CLK_MUX_DIV(_name, _shift, _reg, _shift_div, _table) \
-static PERIPH_MUX(_name, _shift); \
-static PERIPH_DIV(_name, _reg, _shift_div, _table);
-
#define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\
static PERIPH_MUX(_name, _shift); \
static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
@@ -179,13 +223,12 @@ static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
.rate_hw = &rate_##_name.hw, \
}
-#define REF_CLK_MUX_DIV(_name) \
+#define REF_CLK_PM_CPU(_name) \
{ .name = #_name, \
.parent_names = (const char *[]){ "TBG-A-P", \
"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
.num_parents = 4, \
- .mux_hw = &mux_##_name.hw, \
- .rate_hw = &rate_##_name.hw, \
+ .muxrate_hw = &muxrate_##_name.hw, \
}
#define REF_CLK_MUX_DD(_name) \
@@ -215,9 +258,9 @@ PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12);
PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
-PERIPH_CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, clk_table6);
+static PERIPH_PM_CPU(cpu, 22, DIV_SEL0, 28);
-static struct clk_periph_data data_nb[] ={
+static struct clk_periph_data data_nb[] = {
REF_CLK_FULL_DD(mmc),
REF_CLK_FULL_DD(sata_host),
REF_CLK_FULL_DD(sec_at),
@@ -234,7 +277,7 @@ static struct clk_periph_data data_nb[] ={
REF_CLK_FULL(trace),
REF_CLK_FULL(counter),
REF_CLK_FULL_DD(eip97),
- REF_CLK_MUX_DIV(cpu),
+ REF_CLK_PM_CPU(cpu),
{ },
};
@@ -281,7 +324,7 @@ static unsigned int get_div(void __iomem *reg, int shift)
}
static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+ unsigned long parent_rate)
{
struct clk_double_div *double_div = to_clk_double_div(hw);
unsigned int div;
@@ -296,6 +339,222 @@ static const struct clk_ops clk_double_div_ops = {
.recalc_rate = clk_double_div_recalc_rate,
};
+static void armada_3700_pm_dvfs_update_regs(unsigned int load_level,
+ unsigned int *reg,
+ unsigned int *offset)
+{
+ if (load_level <= ARMADA_37XX_DVFS_LOAD_1)
+ *reg = ARMADA_37XX_NB_L0L1;
+ else
+ *reg = ARMADA_37XX_NB_L2L3;
+
+ if (load_level == ARMADA_37XX_DVFS_LOAD_0 ||
+ load_level == ARMADA_37XX_DVFS_LOAD_2)
+ *offset += ARMADA_37XX_NB_CONFIG_SHIFT;
+}
+
+static bool armada_3700_pm_dvfs_is_enabled(struct regmap *base)
+{
+ unsigned int val, reg = ARMADA_37XX_NB_DYN_MOD;
+
+ if (IS_ERR(base))
+ return false;
+
+ regmap_read(base, reg, &val);
+
+ return !!(val & BIT(ARMADA_37XX_NB_DFS_EN));
+}
+
+static unsigned int armada_3700_pm_dvfs_get_cpu_div(struct regmap *base)
+{
+ unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
+ unsigned int offset = ARMADA_37XX_NB_TBG_DIV_OFF;
+ unsigned int load_level, div;
+
+ /*
+ * This function is always called after the function
+ * armada_3700_pm_dvfs_is_enabled, so no need to check again
+ * if the base is valid.
+ */
+ regmap_read(base, reg, &load_level);
+
+ /*
+ * The register and the offset inside this register accessed to
+ * read the current divider depend on the load level
+ */
+ load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
+ armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
+
+ regmap_read(base, reg, &div);
+
+ return (div >> offset) & ARMADA_37XX_NB_TBG_DIV_MASK;
+}
+
+static unsigned int armada_3700_pm_dvfs_get_cpu_parent(struct regmap *base)
+{
+ unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
+ unsigned int offset = ARMADA_37XX_NB_TBG_SEL_OFF;
+ unsigned int load_level, sel;
+
+ /*
+ * This function is always called after the function
+ * armada_3700_pm_dvfs_is_enabled, so no need to check again
+ * if the base is valid
+ */
+ regmap_read(base, reg, &load_level);
+
+ /*
+ * The register and the offset inside this register accessed to
+ * read the current divider depend on the load level
+ */
+ load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
+ armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
+
+ regmap_read(base, reg, &sel);
+
+ return (sel >> offset) & ARMADA_37XX_NB_TBG_SEL_MASK;
+}
+
+static u8 clk_pm_cpu_get_parent(struct clk_hw *hw)
+{
+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
+ int num_parents = clk_hw_get_num_parents(hw);
+ u32 val;
+
+ if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) {
+ val = armada_3700_pm_dvfs_get_cpu_parent(pm_cpu->nb_pm_base);
+ } else {
+ val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux;
+ val &= pm_cpu->mask_mux;
+ }
+
+ if (val >= num_parents)
+ return -EINVAL;
+
+ return val;
+}
+
+static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
+ struct regmap *base = pm_cpu->nb_pm_base;
+ int load_level;
+
+ /*
+ * We set the clock parent only if the DVFS is available but
+ * not enabled.
+ */
+ if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base))
+ return -EINVAL;
+
+ /* Set the parent clock for all the load level */
+ for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
+ unsigned int reg, mask, val,
+ offset = ARMADA_37XX_NB_TBG_SEL_OFF;
+
+ armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
+
+ val = index << offset;
+ mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset;
+ regmap_update_bits(base, reg, mask, val);
+ }
+ return 0;
+}
+
+static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
+ unsigned int div;
+
+ if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base))
+ div = armada_3700_pm_dvfs_get_cpu_div(pm_cpu->nb_pm_base);
+ else
+ div = get_div(pm_cpu->reg_div, pm_cpu->shift_div);
+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
+}
+
+static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
+ struct regmap *base = pm_cpu->nb_pm_base;
+ unsigned int div = *parent_rate / rate;
+ unsigned int load_level;
+ /* only available when DVFS is enabled */
+ if (!armada_3700_pm_dvfs_is_enabled(base))
+ return -EINVAL;
+
+ for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
+ unsigned int reg, val, offset = ARMADA_37XX_NB_TBG_DIV_OFF;
+
+ armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
+
+ regmap_read(base, reg, &val);
+
+ val >>= offset;
+ val &= ARMADA_37XX_NB_TBG_DIV_MASK;
+ if (val == div)
+ /*
+ * We found a load level matching the target
+ * divider, switch to this load level and
+ * return.
+ */
+ return *parent_rate / div;
+ }
+
+ /* We didn't find any valid divider */
+ return -EINVAL;
+}
+
+static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
+ struct regmap *base = pm_cpu->nb_pm_base;
+ unsigned int div = parent_rate / rate;
+ unsigned int load_level;
+
+ /* only available when DVFS is enabled */
+ if (!armada_3700_pm_dvfs_is_enabled(base))
+ return -EINVAL;
+
+ for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
+ unsigned int reg, mask, val,
+ offset = ARMADA_37XX_NB_TBG_DIV_OFF;
+
+ armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
+
+ regmap_read(base, reg, &val);
+ val >>= offset;
+ val &= ARMADA_37XX_NB_TBG_DIV_MASK;
+
+ if (val == div) {
+ /*
+ * We found a load level matching the target
+ * divider, switch to this load level and
+ * return.
+ */
+ reg = ARMADA_37XX_NB_CPU_LOAD;
+ mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
+ regmap_update_bits(base, reg, mask, load_level);
+
+ return rate;
+ }
+ }
+
+ /* We didn't find any valid divider */
+ return -EINVAL;
+}
+
+static const struct clk_ops clk_pm_cpu_ops = {
+ .get_parent = clk_pm_cpu_get_parent,
+ .set_parent = clk_pm_cpu_set_parent,
+ .round_rate = clk_pm_cpu_round_rate,
+ .set_rate = clk_pm_cpu_set_rate,
+ .recalc_rate = clk_pm_cpu_recalc_rate,
+};
+
static const struct of_device_id armada_3700_periph_clock_of_match[] = {
{ .compatible = "marvell,armada-3700-periph-clock-nb",
.data = data_nb, },
@@ -303,6 +562,7 @@ static const struct of_device_id armada_3700_periph_clock_of_match[] = {
.data = data_sb, },
{ }
};
+
static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
void __iomem *reg, spinlock_t *lock,
struct device *dev, struct clk_hw **hw)
@@ -354,10 +614,29 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
}
}
+ if (data->muxrate_hw) {
+ struct clk_pm_cpu *pmcpu_clk;
+ struct clk_hw *muxrate_hw = data->muxrate_hw;
+ struct regmap *map;
+
+ pmcpu_clk = to_clk_pm_cpu(muxrate_hw);
+ pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux;
+ pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div;
+
+ mux_hw = muxrate_hw;
+ rate_hw = muxrate_hw;
+ mux_ops = muxrate_hw->init->ops;
+ rate_ops = muxrate_hw->init->ops;
+
+ map = syscon_regmap_lookup_by_compatible(
+ "marvell,armada-3700-nb-pm");
+ pmcpu_clk->nb_pm_base = map;
+ }
+
*hw = clk_hw_register_composite(dev, data->name, data->parent_names,
- data->num_parents, mux_hw,
- mux_ops, rate_hw, rate_ops,
- gate_hw, gate_ops, CLK_IGNORE_UNUSED);
+ data->num_parents, mux_hw,
+ mux_ops, rate_hw, rate_ops,
+ gate_hw, gate_ops, CLK_IGNORE_UNUSED);
if (IS_ERR(*hw))
return PTR_ERR(*hw);
@@ -406,12 +685,11 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
if (armada_3700_add_composite_clk(&data[i], reg,
&driver_data->lock, dev, hw))
dev_err(dev, "Can't register periph clock %s\n",
- data[i].name);
-
+ data[i].name);
}
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
- driver_data->hw_data);
+ driver_data->hw_data);
if (ret) {
for (i = 0; i < num_periph; i++)
clk_hw_unregister(driver_data->hw_data->hws[i]);
diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
index 7b359af..b669a5c 100644
--- a/drivers/clk/nxp/clk-lpc32xx.c
+++ b/drivers/clk/nxp/clk-lpc32xx.c
@@ -526,7 +526,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
!(pll_is_valid(parent_rate, 1, 1000000, 20000000)
&& pll_is_valid(cco_rate, 1, 156000000, 320000000)
&& pll_is_valid(ref_rate, 1, 1000000, 27000000)))
- pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu",
+ pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu\n",
clk_hw_get_name(hw),
parent_rate, cco_rate, ref_rate);
@@ -1505,7 +1505,7 @@ static void __init lpc32xx_clk_init(struct device_node *np)
return;
}
if (clk_get_rate(clk_32k) != 32768) {
- pr_err("invalid clock rate of external 32KHz oscillator");
+ pr_err("invalid clock rate of external 32KHz oscillator\n");
return;
}
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9f6c278..20b5d6f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -196,3 +196,12 @@
Support for the multimedia clock controller on msm8996 devices.
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+
+config SPMI_PMIC_CLKDIV
+ tristate "SPMI PMIC clkdiv Support"
+ depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
+ help
+ This driver supports the clkdiv functionality on the Qualcomm
+ Technologies, Inc. SPMI PMIC. It configures the frequency of
+ clkdiv outputs of the PMIC. These clocks are typically wired
+ through alternate functions on GPIO pins.
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 26410d3..602af38 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -34,3 +34,4 @@
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
+obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 47a1da3..6d04cd9 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -20,7 +20,7 @@
#include "clk-alpha-pll.h"
#include "common.h"
-#define PLL_MODE 0x00
+#define PLL_MODE(p) ((p)->offset + 0x0)
# define PLL_OUTCTRL BIT(0)
# define PLL_BYPASSNL BIT(1)
# define PLL_RESET_N BIT(2)
@@ -32,35 +32,87 @@
# define PLL_VOTE_FSM_ENA BIT(20)
# define PLL_FSM_ENA BIT(20)
# define PLL_VOTE_FSM_RESET BIT(21)
+# define PLL_UPDATE BIT(22)
+# define PLL_UPDATE_BYPASS BIT(23)
# define PLL_OFFLINE_ACK BIT(28)
+# define ALPHA_PLL_ACK_LATCH BIT(29)
# define PLL_ACTIVE_FLAG BIT(30)
# define PLL_LOCK_DET BIT(31)
-#define PLL_L_VAL 0x04
-#define PLL_ALPHA_VAL 0x08
-#define PLL_ALPHA_VAL_U 0x0c
+#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
+#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
+#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
-#define PLL_USER_CTL 0x10
+#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
# define PLL_POST_DIV_SHIFT 8
-# define PLL_POST_DIV_MASK 0xf
+# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
# define PLL_ALPHA_EN BIT(24)
+# define PLL_ALPHA_MODE BIT(25)
# define PLL_VCO_SHIFT 20
# define PLL_VCO_MASK 0x3
-#define PLL_USER_CTL_U 0x14
+#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
-#define PLL_CONFIG_CTL 0x18
-#define PLL_CONFIG_CTL_U 0x20
-#define PLL_TEST_CTL 0x1c
-#define PLL_TEST_CTL_U 0x20
-#define PLL_STATUS 0x24
+#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
+#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
+#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
+#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
+#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
+
+const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
+ [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL_U] = 0x0c,
+ [PLL_OFF_USER_CTL] = 0x10,
+ [PLL_OFF_USER_CTL_U] = 0x14,
+ [PLL_OFF_CONFIG_CTL] = 0x18,
+ [PLL_OFF_TEST_CTL] = 0x1c,
+ [PLL_OFF_TEST_CTL_U] = 0x20,
+ [PLL_OFF_STATUS] = 0x24,
+ },
+ [CLK_ALPHA_PLL_TYPE_HUAYRA] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_USER_CTL] = 0x10,
+ [PLL_OFF_CONFIG_CTL] = 0x14,
+ [PLL_OFF_CONFIG_CTL_U] = 0x18,
+ [PLL_OFF_TEST_CTL] = 0x1c,
+ [PLL_OFF_TEST_CTL_U] = 0x20,
+ [PLL_OFF_STATUS] = 0x24,
+ },
+ [CLK_ALPHA_PLL_TYPE_BRAMMO] = {
+ [PLL_OFF_L_VAL] = 0x04,
+ [PLL_OFF_ALPHA_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL_U] = 0x0c,
+ [PLL_OFF_USER_CTL] = 0x10,
+ [PLL_OFF_CONFIG_CTL] = 0x18,
+ [PLL_OFF_TEST_CTL] = 0x1c,
+ [PLL_OFF_STATUS] = 0x24,
+ },
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
/*
* Even though 40 bits are present, use only 32 for ease of calculation.
*/
#define ALPHA_REG_BITWIDTH 40
-#define ALPHA_BITWIDTH 32
-#define ALPHA_16BIT_MASK 0xffff
+#define ALPHA_REG_16BIT_WIDTH 16
+#define ALPHA_BITWIDTH 32U
+#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
+
+#define PLL_HUAYRA_M_WIDTH 8
+#define PLL_HUAYRA_M_SHIFT 8
+#define PLL_HUAYRA_M_MASK 0xff
+#define PLL_HUAYRA_N_SHIFT 0
+#define PLL_HUAYRA_N_MASK 0xff
+#define PLL_HUAYRA_ALPHA_WIDTH 16
+
+#define pll_alpha_width(p) \
+ ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
+ ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
+
+#define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
#define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
struct clk_alpha_pll, clkr)
@@ -71,18 +123,17 @@
static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
const char *action)
{
- u32 val, off;
+ u32 val;
int count;
int ret;
const char *name = clk_hw_get_name(&pll->clkr.hw);
- off = pll->offset;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
for (count = 100; count > 0; count--) {
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
if (inverse && !(val & mask))
@@ -109,16 +160,30 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
#define wait_for_pll_offline(pll) \
wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
+#define wait_for_pll_update(pll) \
+ wait_for_pll(pll, PLL_UPDATE, 1, "update")
+
+#define wait_for_pll_update_ack_set(pll) \
+ wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
+
+#define wait_for_pll_update_ack_clear(pll) \
+ wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
+
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
u32 val, mask;
- u32 off = pll->offset;
- regmap_write(regmap, off + PLL_L_VAL, config->l);
- regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
- regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
- regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val);
+ regmap_write(regmap, PLL_L_VAL(pll), config->l);
+ regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
+ regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
+
+ if (pll_has_64bit_config(pll))
+ regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
+ config->config_ctl_hi_val);
+
+ if (pll_alpha_width(pll) > 32)
+ regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
val = config->main_output_mask;
val |= config->aux_output_mask;
@@ -127,6 +192,8 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
val |= config->pre_div_val;
val |= config->post_div_val;
val |= config->vco_val;
+ val |= config->alpha_en_mask;
+ val |= config->alpha_mode_mask;
mask = config->main_output_mask;
mask |= config->aux_output_mask;
@@ -136,20 +203,19 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
mask |= config->post_div_mask;
mask |= config->vco_mask;
- regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val);
+ regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
if (pll->flags & SUPPORTS_FSM_MODE)
- qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0);
+ qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
}
static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
{
int ret;
- u32 val, off;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 val;
- off = pll->offset;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
@@ -158,7 +224,7 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
if (pll->flags & SUPPORTS_OFFLINE_REQ)
val &= ~PLL_OFFLINE_REQ;
- ret = regmap_write(pll->clkr.regmap, off + PLL_MODE, val);
+ ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
if (ret)
return ret;
@@ -171,16 +237,15 @@ static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
{
int ret;
- u32 val, off;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 val;
- off = pll->offset;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return;
if (pll->flags & SUPPORTS_OFFLINE_REQ) {
- ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
if (ret)
return;
@@ -191,7 +256,7 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
}
/* Disable hwfsm */
- ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_FSM_ENA, 0);
if (ret)
return;
@@ -202,11 +267,10 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
static int pll_is_enabled(struct clk_hw *hw, u32 mask)
{
int ret;
- u32 val, off;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 val;
- off = pll->offset;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
@@ -227,12 +291,10 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- u32 val, mask, off;
-
- off = pll->offset;
+ u32 val, mask;
mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return ret;
@@ -248,7 +310,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
if ((val & mask) == mask)
return 0;
- ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_BYPASSNL, PLL_BYPASSNL);
if (ret)
return ret;
@@ -260,7 +322,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
mb();
udelay(5);
- ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_RESET_N, PLL_RESET_N);
if (ret)
return ret;
@@ -269,7 +331,7 @@ static int clk_alpha_pll_enable(struct clk_hw *hw)
if (ret)
return ret;
- ret = regmap_update_bits(pll->clkr.regmap, off + PLL_MODE,
+ ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
PLL_OUTCTRL, PLL_OUTCTRL);
/* Ensure that the write above goes through before returning. */
@@ -281,11 +343,9 @@ static void clk_alpha_pll_disable(struct clk_hw *hw)
{
int ret;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- u32 val, mask, off;
+ u32 val, mask;
- off = pll->offset;
-
- ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+ ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
if (ret)
return;
@@ -296,23 +356,25 @@ static void clk_alpha_pll_disable(struct clk_hw *hw)
}
mask = PLL_OUTCTRL;
- regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
/* Delay of 2 output clock ticks required until output is disabled */
mb();
udelay(1);
mask = PLL_RESET_N | PLL_BYPASSNL;
- regmap_update_bits(pll->clkr.regmap, off + PLL_MODE, mask, 0);
-}
-
-static unsigned long alpha_pll_calc_rate(u64 prate, u32 l, u32 a)
-{
- return (prate * l) + ((prate * a) >> ALPHA_BITWIDTH);
+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
}
static unsigned long
-alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
+alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
+{
+ return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
+}
+
+static unsigned long
+alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
+ u32 alpha_width)
{
u64 remainder;
u64 quotient;
@@ -327,14 +389,15 @@ alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
}
/* Upper ALPHA_BITWIDTH bits of Alpha */
- quotient = remainder << ALPHA_BITWIDTH;
+ quotient = remainder << ALPHA_SHIFT(alpha_width);
+
remainder = do_div(quotient, prate);
if (remainder)
quotient++;
*a = quotient;
- return alpha_pll_calc_rate(prate, *l, *a);
+ return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
}
static const struct pll_vco *
@@ -356,71 +419,138 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
u32 l, low, high, ctl;
u64 a = 0, prate = parent_rate;
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- u32 off = pll->offset;
+ u32 alpha_width = pll_alpha_width(pll);
- regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);
+ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
- regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl);
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
if (ctl & PLL_ALPHA_EN) {
- regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low);
- if (pll->flags & SUPPORTS_16BIT_ALPHA) {
- a = low & ALPHA_16BIT_MASK;
- } else {
- regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U,
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
+ if (alpha_width > 32) {
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
&high);
a = (u64)high << 32 | low;
- a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
+ } else {
+ a = low & GENMASK(alpha_width - 1, 0);
}
+
+ if (alpha_width > ALPHA_BITWIDTH)
+ a >>= alpha_width - ALPHA_BITWIDTH;
}
- return alpha_pll_calc_rate(prate, l, a);
+ return alpha_pll_calc_rate(prate, l, a, alpha_width);
+}
+
+static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
+ int (*is_enabled)(struct clk_hw *))
+{
+ int ret;
+ u32 mode;
+
+ if (!is_enabled(&pll->clkr.hw) ||
+ !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
+ return 0;
+
+ regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
+
+ /* Latch the input to the PLL */
+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
+ PLL_UPDATE);
+
+ /* Wait for 2 reference cycle before checking ACK bit */
+ udelay(1);
+
+ /*
+ * PLL will latch the new L, Alpha and freq control word.
+ * PLL will respond by raising PLL_ACK_LATCH output when new programming
+ * has been latched in and PLL is being updated. When
+ * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
+ * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
+ */
+ if (mode & PLL_UPDATE_BYPASS) {
+ ret = wait_for_pll_update_ack_set(pll);
+ if (ret)
+ return ret;
+
+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
+ } else {
+ ret = wait_for_pll_update(pll);
+ if (ret)
+ return ret;
+ }
+
+ ret = wait_for_pll_update_ack_clear(pll);
+ if (ret)
+ return ret;
+
+ /* Wait for PLL output to stabilize */
+ udelay(10);
+
+ return 0;
+}
+
+static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate,
+ int (*is_enabled)(struct clk_hw *))
+{
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ const struct pll_vco *vco;
+ u32 l, alpha_width = pll_alpha_width(pll);
+ u64 a;
+
+ rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
+ vco = alpha_pll_find_vco(pll, rate);
+ if (pll->vco_table && !vco) {
+ pr_err("alpha pll not in a valid vco range\n");
+ return -EINVAL;
+ }
+
+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+
+ if (alpha_width > ALPHA_BITWIDTH)
+ a <<= alpha_width - ALPHA_BITWIDTH;
+
+ if (alpha_width > 32)
+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
+
+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+
+ if (vco) {
+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_VCO_MASK << PLL_VCO_SHIFT,
+ vco->val << PLL_VCO_SHIFT);
+ }
+
+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_ALPHA_EN, PLL_ALPHA_EN);
+
+ return clk_alpha_pll_update_latch(pll, is_enabled);
}
static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
- struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- const struct pll_vco *vco;
- u32 l, off = pll->offset;
- u64 a;
+ return __clk_alpha_pll_set_rate(hw, rate, prate,
+ clk_alpha_pll_is_enabled);
+}
- rate = alpha_pll_round_rate(rate, prate, &l, &a);
- vco = alpha_pll_find_vco(pll, rate);
- if (!vco) {
- pr_err("alpha pll not in a valid vco range\n");
- return -EINVAL;
- }
-
- regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
-
- if (pll->flags & SUPPORTS_16BIT_ALPHA) {
- regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL,
- a & ALPHA_16BIT_MASK);
- } else {
- a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
- regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
- }
-
- regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
- PLL_VCO_MASK << PLL_VCO_SHIFT,
- vco->val << PLL_VCO_SHIFT);
-
- regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL, PLL_ALPHA_EN,
- PLL_ALPHA_EN);
-
- return 0;
+static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ return __clk_alpha_pll_set_rate(hw, rate, prate,
+ clk_alpha_pll_hwfsm_is_enabled);
}
static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- u32 l;
+ u32 l, alpha_width = pll_alpha_width(pll);
u64 a;
unsigned long min_freq, max_freq;
- rate = alpha_pll_round_rate(rate, *prate, &l, &a);
- if (alpha_pll_find_vco(pll, rate))
+ rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
+ if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
return rate;
min_freq = pll->vco_table[0].min_freq;
@@ -429,6 +559,158 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
return clamp(rate, min_freq, max_freq);
}
+static unsigned long
+alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
+{
+ /*
+ * a contains 16 bit alpha_val in two’s compliment number in the range
+ * of [-0.5, 0.5).
+ */
+ if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
+ l -= 1;
+
+ return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
+}
+
+static unsigned long
+alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
+ u32 *l, u32 *a)
+{
+ u64 remainder;
+ u64 quotient;
+
+ quotient = rate;
+ remainder = do_div(quotient, prate);
+ *l = quotient;
+
+ if (!remainder) {
+ *a = 0;
+ return rate;
+ }
+
+ quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
+ remainder = do_div(quotient, prate);
+
+ if (remainder)
+ quotient++;
+
+ /*
+ * alpha_val should be in two’s compliment number in the range
+ * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
+ * since alpha value will be subtracted in this case.
+ */
+ if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
+ *l += 1;
+
+ *a = quotient;
+ return alpha_huayra_pll_calc_rate(prate, *l, *a);
+}
+
+static unsigned long
+alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ u64 rate = parent_rate, tmp;
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 l, alpha = 0, ctl, alpha_m, alpha_n;
+
+ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
+
+ if (ctl & PLL_ALPHA_EN) {
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
+ /*
+ * Depending upon alpha_mode, it can be treated as M/N value or
+ * as a two’s compliment number. When alpha_mode=1,
+ * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
+ *
+ * Fout=FIN*(L+(M/N))
+ *
+ * M is a signed number (-128 to 127) and N is unsigned
+ * (0 to 255). M/N has to be within +/-0.5.
+ *
+ * When alpha_mode=0, it is a two’s compliment number in the
+ * range [-0.5, 0.5).
+ *
+ * Fout=FIN*(L+(alpha_val)/2^16)
+ *
+ * where alpha_val is two’s compliment number.
+ */
+ if (!(ctl & PLL_ALPHA_MODE))
+ return alpha_huayra_pll_calc_rate(rate, l, alpha);
+
+ alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
+ alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
+
+ rate *= l;
+ tmp = parent_rate;
+ if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
+ alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
+ tmp *= alpha_m;
+ do_div(tmp, alpha_n);
+ rate -= tmp;
+ } else {
+ tmp *= alpha_m;
+ do_div(tmp, alpha_n);
+ rate += tmp;
+ }
+
+ return rate;
+ }
+
+ return alpha_huayra_pll_calc_rate(rate, l, alpha);
+}
+
+static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 l, a, ctl, cur_alpha = 0;
+
+ rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
+
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
+
+ if (ctl & PLL_ALPHA_EN)
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
+
+ /*
+ * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
+ * without having to go through the power on sequence.
+ */
+ if (clk_alpha_pll_is_enabled(hw)) {
+ if (cur_alpha != a) {
+ pr_err("clock needs to be gated %s\n",
+ clk_hw_get_name(hw));
+ return -EBUSY;
+ }
+
+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+ /* Ensure that the write above goes to detect L val change. */
+ mb();
+ return wait_for_pll_enable_lock(pll);
+ }
+
+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+
+ if (a == 0)
+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_ALPHA_EN, 0x0);
+ else
+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
+
+ return 0;
+}
+
+static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ u32 l, a;
+
+ return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
+}
+
const struct clk_ops clk_alpha_pll_ops = {
.enable = clk_alpha_pll_enable,
.disable = clk_alpha_pll_disable,
@@ -439,13 +721,23 @@ const struct clk_ops clk_alpha_pll_ops = {
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
+const struct clk_ops clk_alpha_pll_huayra_ops = {
+ .enable = clk_alpha_pll_enable,
+ .disable = clk_alpha_pll_disable,
+ .is_enabled = clk_alpha_pll_is_enabled,
+ .recalc_rate = alpha_pll_huayra_recalc_rate,
+ .round_rate = alpha_pll_huayra_round_rate,
+ .set_rate = alpha_pll_huayra_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
+
const struct clk_ops clk_alpha_pll_hwfsm_ops = {
.enable = clk_alpha_pll_hwfsm_enable,
.disable = clk_alpha_pll_hwfsm_disable,
.is_enabled = clk_alpha_pll_hwfsm_is_enabled,
.recalc_rate = clk_alpha_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
- .set_rate = clk_alpha_pll_set_rate,
+ .set_rate = clk_alpha_pll_hwfsm_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
@@ -455,10 +747,10 @@ clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
u32 ctl;
- regmap_read(pll->clkr.regmap, pll->offset + PLL_USER_CTL, &ctl);
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
ctl >>= PLL_POST_DIV_SHIFT;
- ctl &= PLL_POST_DIV_MASK;
+ ctl &= PLL_POST_DIV_MASK(pll);
return parent_rate >> fls(ctl);
}
@@ -472,16 +764,48 @@ static const struct clk_div_table clk_alpha_div_table[] = {
{ }
};
+static const struct clk_div_table clk_alpha_2bit_div_table[] = {
+ { 0x0, 1 },
+ { 0x1, 2 },
+ { 0x3, 4 },
+ { }
+};
+
static long
clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+ const struct clk_div_table *table;
- return divider_round_rate(hw, rate, prate, clk_alpha_div_table,
+ if (pll->width == 2)
+ table = clk_alpha_2bit_div_table;
+ else
+ table = clk_alpha_div_table;
+
+ return divider_round_rate(hw, rate, prate, table,
pll->width, CLK_DIVIDER_POWER_OF_TWO);
}
+static long
+clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+ u32 ctl, div;
+
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
+
+ ctl >>= PLL_POST_DIV_SHIFT;
+ ctl &= BIT(pll->width) - 1;
+ div = 1 << fls(ctl);
+
+ if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
+ *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
+
+ return DIV_ROUND_UP_ULL((u64)*prate, div);
+}
+
static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -491,8 +815,8 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
/* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
- return regmap_update_bits(pll->clkr.regmap, pll->offset + PLL_USER_CTL,
- PLL_POST_DIV_MASK << PLL_POST_DIV_SHIFT,
+ return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
div << PLL_POST_DIV_SHIFT);
}
@@ -502,3 +826,9 @@ const struct clk_ops clk_alpha_pll_postdiv_ops = {
.set_rate = clk_alpha_pll_postdiv_set_rate,
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
+
+const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
+ .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
+ .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index d6e1ee2..7593e8a 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -17,6 +17,30 @@
#include <linux/clk-provider.h>
#include "clk-regmap.h"
+/* Alpha PLL types */
+enum {
+ CLK_ALPHA_PLL_TYPE_DEFAULT,
+ CLK_ALPHA_PLL_TYPE_HUAYRA,
+ CLK_ALPHA_PLL_TYPE_BRAMMO,
+ CLK_ALPHA_PLL_TYPE_MAX,
+};
+
+enum {
+ PLL_OFF_L_VAL,
+ PLL_OFF_ALPHA_VAL,
+ PLL_OFF_ALPHA_VAL_U,
+ PLL_OFF_USER_CTL,
+ PLL_OFF_USER_CTL_U,
+ PLL_OFF_CONFIG_CTL,
+ PLL_OFF_CONFIG_CTL_U,
+ PLL_OFF_TEST_CTL,
+ PLL_OFF_TEST_CTL_U,
+ PLL_OFF_STATUS,
+ PLL_OFF_MAX_REGS
+};
+
+extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
+
struct pll_vco {
unsigned long min_freq;
unsigned long max_freq;
@@ -27,16 +51,18 @@ struct pll_vco {
* struct clk_alpha_pll - phase locked loop (PLL)
* @offset: base address of registers
* @vco_table: array of VCO settings
+ * @regs: alpha pll register map (see @clk_alpha_pll_regs)
* @clkr: regmap clock handle
*/
struct clk_alpha_pll {
u32 offset;
+ const u8 *regs;
const struct pll_vco *vco_table;
size_t num_vco;
#define SUPPORTS_OFFLINE_REQ BIT(0)
-#define SUPPORTS_16BIT_ALPHA BIT(1)
#define SUPPORTS_FSM_MODE BIT(2)
+#define SUPPORTS_DYNAMIC_UPDATE BIT(3)
u8 flags;
struct clk_regmap clkr;
@@ -45,12 +71,14 @@ struct clk_alpha_pll {
/**
* struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
* @offset: base address of registers
+ * @regs: alpha pll register map (see @clk_alpha_pll_regs)
* @width: width of post-divider
* @clkr: regmap clock handle
*/
struct clk_alpha_pll_postdiv {
u32 offset;
u8 width;
+ const u8 *regs;
struct clk_regmap clkr;
};
@@ -58,12 +86,15 @@ struct clk_alpha_pll_postdiv {
struct alpha_pll_config {
u32 l;
u32 alpha;
+ u32 alpha_hi;
u32 config_ctl_val;
u32 config_ctl_hi_val;
u32 main_output_mask;
u32 aux_output_mask;
u32 aux2_output_mask;
u32 early_output_mask;
+ u32 alpha_en_mask;
+ u32 alpha_mode_mask;
u32 pre_div_val;
u32 pre_div_mask;
u32 post_div_val;
@@ -75,6 +106,8 @@ struct alpha_pll_config {
extern const struct clk_ops clk_alpha_pll_ops;
extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ops;
+extern const struct clk_ops clk_alpha_pll_huayra_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index a249545..2a7489a 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -26,16 +26,6 @@ struct freq_tbl {
};
/**
- * struct parent_map - map table for PLL source select configuration values
- * @src: source PLL
- * @cfg: configuration value
- */
-struct parent_map {
- u8 src;
- u8 cfg;
-};
-
-/**
* struct mn - M/N:D counter
* @mnctr_en_bit: bit to enable mn counter
* @mnctr_reset_bit: bit to assert mn counter reset
diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-regmap-divider.c
index 5348491..6cf9005 100644
--- a/drivers/clk/qcom/clk-regmap-divider.c
+++ b/drivers/clk/qcom/clk-regmap-divider.c
@@ -23,6 +23,29 @@ static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
}
+static long div_round_ro_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_regmap_div *divider = to_clk_regmap_div(hw);
+ struct clk_regmap *clkr = ÷r->clkr;
+ u32 div;
+ struct clk_hw *hw_parent = clk_hw_get_parent(hw);
+
+ regmap_read(clkr->regmap, divider->reg, &div);
+ div >>= divider->shift;
+ div &= BIT(divider->width) - 1;
+ div += 1;
+
+ if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
+ if (!hw_parent)
+ return -EINVAL;
+
+ *prate = clk_hw_round_rate(hw_parent, rate * div);
+ }
+
+ return DIV_ROUND_UP_ULL((u64)*prate, div);
+}
+
static long div_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
@@ -68,3 +91,9 @@ const struct clk_ops clk_regmap_div_ops = {
.recalc_rate = div_recalc_rate,
};
EXPORT_SYMBOL_GPL(clk_regmap_div_ops);
+
+const struct clk_ops clk_regmap_div_ro_ops = {
+ .round_rate = div_round_ro_rate,
+ .recalc_rate = div_recalc_rate,
+};
+EXPORT_SYMBOL_GPL(clk_regmap_div_ro_ops);
diff --git a/drivers/clk/qcom/clk-regmap-divider.h b/drivers/clk/qcom/clk-regmap-divider.h
index fc4492e..8c39c27 100644
--- a/drivers/clk/qcom/clk-regmap-divider.h
+++ b/drivers/clk/qcom/clk-regmap-divider.h
@@ -25,5 +25,6 @@ struct clk_regmap_div {
};
extern const struct clk_ops clk_regmap_div_ops;
+extern const struct clk_ops clk_regmap_div_ro_ops;
#endif
diff --git a/drivers/clk/qcom/clk-regmap-mux.c b/drivers/clk/qcom/clk-regmap-mux.c
index cae3071..0f3a1bd 100644
--- a/drivers/clk/qcom/clk-regmap-mux.c
+++ b/drivers/clk/qcom/clk-regmap-mux.c
@@ -35,6 +35,9 @@ static u8 mux_get_parent(struct clk_hw *hw)
val >>= mux->shift;
val &= mask;
+ if (mux->parent_map)
+ return qcom_find_src_index(hw, mux->parent_map, val);
+
return val;
}
@@ -45,6 +48,9 @@ static int mux_set_parent(struct clk_hw *hw, u8 index)
unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift);
unsigned int val;
+ if (mux->parent_map)
+ index = mux->parent_map[index].cfg;
+
val = index;
val <<= mux->shift;
diff --git a/drivers/clk/qcom/clk-regmap-mux.h b/drivers/clk/qcom/clk-regmap-mux.h
index 5cec761..7797cdd 100644
--- a/drivers/clk/qcom/clk-regmap-mux.h
+++ b/drivers/clk/qcom/clk-regmap-mux.h
@@ -16,11 +16,13 @@
#include <linux/clk-provider.h>
#include "clk-regmap.h"
+#include "common.h"
struct clk_regmap_mux {
u32 reg;
u32 shift;
u32 width;
+ const struct parent_map *parent_map;
struct clk_regmap clkr;
};
diff --git a/drivers/clk/qcom/clk-spmi-pmic-div.c b/drivers/clk/qcom/clk-spmi-pmic-div.c
new file mode 100644
index 0000000..8672ab8
--- /dev/null
+++ b/drivers/clk/qcom/clk-spmi-pmic-div.c
@@ -0,0 +1,302 @@
+/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/log2.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#define REG_DIV_CTL1 0x43
+#define DIV_CTL1_DIV_FACTOR_MASK GENMASK(2, 0)
+
+#define REG_EN_CTL 0x46
+#define REG_EN_MASK BIT(7)
+
+struct clkdiv {
+ struct regmap *regmap;
+ u16 base;
+ spinlock_t lock;
+
+ struct clk_hw hw;
+ unsigned int cxo_period_ns;
+};
+
+static inline struct clkdiv *to_clkdiv(struct clk_hw *hw)
+{
+ return container_of(hw, struct clkdiv, hw);
+}
+
+static inline unsigned int div_factor_to_div(unsigned int div_factor)
+{
+ if (!div_factor)
+ div_factor = 1;
+
+ return 1 << (div_factor - 1);
+}
+
+static inline unsigned int div_to_div_factor(unsigned int div)
+{
+ return min(ilog2(div) + 1, 7);
+}
+
+static bool is_spmi_pmic_clkdiv_enabled(struct clkdiv *clkdiv)
+{
+ unsigned int val = 0;
+
+ regmap_read(clkdiv->regmap, clkdiv->base + REG_EN_CTL, &val);
+
+ return val & REG_EN_MASK;
+}
+
+static int
+__spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable,
+ unsigned int div_factor)
+{
+ int ret;
+ unsigned int ns = clkdiv->cxo_period_ns;
+ unsigned int div = div_factor_to_div(div_factor);
+
+ ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_EN_CTL,
+ REG_EN_MASK, enable ? REG_EN_MASK : 0);
+ if (ret)
+ return ret;
+
+ if (enable)
+ ndelay((2 + 3 * div) * ns);
+ else
+ ndelay(3 * div * ns);
+
+ return 0;
+}
+
+static int spmi_pmic_clkdiv_set_enable_state(struct clkdiv *clkdiv, bool enable)
+{
+ unsigned int div_factor;
+
+ regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
+ div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
+
+ return __spmi_pmic_clkdiv_set_enable_state(clkdiv, enable, div_factor);
+}
+
+static int clk_spmi_pmic_div_enable(struct clk_hw *hw)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned long flags;
+ int ret;
+
+ spin_lock_irqsave(&clkdiv->lock, flags);
+ ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, true);
+ spin_unlock_irqrestore(&clkdiv->lock, flags);
+
+ return ret;
+}
+
+static void clk_spmi_pmic_div_disable(struct clk_hw *hw)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(&clkdiv->lock, flags);
+ spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
+ spin_unlock_irqrestore(&clkdiv->lock, flags);
+}
+
+static long clk_spmi_pmic_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned int div, div_factor;
+
+ div = DIV_ROUND_UP(*parent_rate, rate);
+ div_factor = div_to_div_factor(div);
+ div = div_factor_to_div(div_factor);
+
+ return *parent_rate / div;
+}
+
+static unsigned long
+clk_spmi_pmic_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned int div_factor;
+
+ regmap_read(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1, &div_factor);
+ div_factor &= DIV_CTL1_DIV_FACTOR_MASK;
+
+ return parent_rate / div_factor_to_div(div_factor);
+}
+
+static int clk_spmi_pmic_div_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clkdiv *clkdiv = to_clkdiv(hw);
+ unsigned int div_factor = div_to_div_factor(parent_rate / rate);
+ unsigned long flags;
+ bool enabled;
+ int ret;
+
+ spin_lock_irqsave(&clkdiv->lock, flags);
+ enabled = is_spmi_pmic_clkdiv_enabled(clkdiv);
+ if (enabled) {
+ ret = spmi_pmic_clkdiv_set_enable_state(clkdiv, false);
+ if (ret)
+ goto unlock;
+ }
+
+ ret = regmap_update_bits(clkdiv->regmap, clkdiv->base + REG_DIV_CTL1,
+ DIV_CTL1_DIV_FACTOR_MASK, div_factor);
+ if (ret)
+ goto unlock;
+
+ if (enabled)
+ ret = __spmi_pmic_clkdiv_set_enable_state(clkdiv, true,
+ div_factor);
+
+unlock:
+ spin_unlock_irqrestore(&clkdiv->lock, flags);
+
+ return ret;
+}
+
+static const struct clk_ops clk_spmi_pmic_div_ops = {
+ .enable = clk_spmi_pmic_div_enable,
+ .disable = clk_spmi_pmic_div_disable,
+ .set_rate = clk_spmi_pmic_div_set_rate,
+ .recalc_rate = clk_spmi_pmic_div_recalc_rate,
+ .round_rate = clk_spmi_pmic_div_round_rate,
+};
+
+struct spmi_pmic_div_clk_cc {
+ int nclks;
+ struct clkdiv clks[];
+};
+
+static struct clk_hw *
+spmi_pmic_div_clk_hw_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct spmi_pmic_div_clk_cc *cc = data;
+ int idx = clkspec->args[0] - 1; /* Start at 1 instead of 0 */
+
+ if (idx < 0 || idx >= cc->nclks) {
+ pr_err("%s: index value %u is invalid; allowed range [1, %d]\n",
+ __func__, clkspec->args[0], cc->nclks);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return &cc->clks[idx].hw;
+}
+
+static int spmi_pmic_clkdiv_probe(struct platform_device *pdev)
+{
+ struct spmi_pmic_div_clk_cc *cc;
+ struct clk_init_data init = {};
+ struct clkdiv *clkdiv;
+ struct clk *cxo;
+ struct regmap *regmap;
+ struct device *dev = &pdev->dev;
+ struct device_node *of_node = dev->of_node;
+ const char *parent_name;
+ int nclks, i, ret, cxo_hz;
+ char name[20];
+ u32 start;
+
+ ret = of_property_read_u32(of_node, "reg", &start);
+ if (ret < 0) {
+ dev_err(dev, "reg property reading failed\n");
+ return ret;
+ }
+
+ regmap = dev_get_regmap(dev->parent, NULL);
+ if (!regmap) {
+ dev_err(dev, "Couldn't get parent's regmap\n");
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32(of_node, "qcom,num-clkdivs", &nclks);
+ if (ret < 0) {
+ dev_err(dev, "qcom,num-clkdivs property reading failed, ret=%d\n",
+ ret);
+ return ret;
+ }
+
+ if (!nclks)
+ return -EINVAL;
+
+ cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*cc->clks) * nclks,
+ GFP_KERNEL);
+ if (!cc)
+ return -ENOMEM;
+ cc->nclks = nclks;
+
+ cxo = clk_get(dev, "xo");
+ if (IS_ERR(cxo)) {
+ ret = PTR_ERR(cxo);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "failed to get xo clock\n");
+ return ret;
+ }
+ cxo_hz = clk_get_rate(cxo);
+ clk_put(cxo);
+
+ parent_name = of_clk_get_parent_name(of_node, 0);
+ if (!parent_name) {
+ dev_err(dev, "missing parent clock\n");
+ return -ENODEV;
+ }
+
+ init.name = name;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+ init.ops = &clk_spmi_pmic_div_ops;
+
+ for (i = 0, clkdiv = cc->clks; i < nclks; i++) {
+ snprintf(name, sizeof(name), "div_clk%d", i + 1);
+
+ spin_lock_init(&clkdiv[i].lock);
+ clkdiv[i].base = start + i * 0x100;
+ clkdiv[i].regmap = regmap;
+ clkdiv[i].cxo_period_ns = NSEC_PER_SEC / cxo_hz;
+ clkdiv[i].hw.init = &init;
+
+ ret = devm_clk_hw_register(dev, &clkdiv[i].hw);
+ if (ret)
+ return ret;
+ }
+
+ return devm_of_clk_add_hw_provider(dev, spmi_pmic_div_clk_hw_get, cc);
+}
+
+static const struct of_device_id spmi_pmic_clkdiv_match_table[] = {
+ { .compatible = "qcom,spmi-clkdiv" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, spmi_pmic_clkdiv_match_table);
+
+static struct platform_driver spmi_pmic_clkdiv_driver = {
+ .driver = {
+ .name = "qcom,spmi-pmic-clkdiv",
+ .of_match_table = spmi_pmic_clkdiv_match_table,
+ },
+ .probe = spmi_pmic_clkdiv_probe,
+};
+module_platform_driver(spmi_pmic_clkdiv_driver);
+
+MODULE_DESCRIPTION("QCOM SPMI PMIC clkdiv driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 23c1927..00196ee 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -20,7 +20,6 @@ struct qcom_reset_map;
struct regmap;
struct freq_tbl;
struct clk_hw;
-struct parent_map;
#define PLL_LOCK_COUNT_SHIFT 8
#define PLL_LOCK_COUNT_MASK 0x3f
@@ -39,6 +38,16 @@ struct qcom_cc_desc {
size_t num_gdscs;
};
+/**
+ * struct parent_map - map table for source select configuration values
+ * @src: source
+ * @cfg: configuration value
+ */
+struct parent_map {
+ u8 src;
+ u8 cfg;
+};
+
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
unsigned long rate);
extern const struct freq_tbl *qcom_find_freq_floor(const struct freq_tbl *f,
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 0f735d3..0462f4a 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -28,6 +28,8 @@
#include "clk-rcg.h"
#include "clk-branch.h"
#include "clk-alpha-pll.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
#include "reset.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -36,6 +38,24 @@ enum {
P_XO,
P_GPLL0,
P_GPLL0_DIV2,
+ P_GPLL2,
+ P_GPLL4,
+ P_GPLL6,
+ P_SLEEP_CLK,
+ P_PCIE20_PHY0_PIPE,
+ P_PCIE20_PHY1_PIPE,
+ P_USB3PHY_0_PIPE,
+ P_USB3PHY_1_PIPE,
+ P_UBI32_PLL,
+ P_NSS_CRYPTO_PLL,
+ P_BIAS_PLL,
+ P_BIAS_PLL_NSS_NOC,
+ P_UNIPHY0_RX,
+ P_UNIPHY0_TX,
+ P_UNIPHY1_RX,
+ P_UNIPHY1_TX,
+ P_UNIPHY2_RX,
+ P_UNIPHY2_TX,
};
static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
@@ -50,8 +70,345 @@ static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
{ P_GPLL0_DIV2, 4 },
};
+static const char * const gcc_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll2",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL2, 2 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const char * const gcc_xo_gpll0_sleep_clk[] = {
+ "xo",
+ "gpll0",
+ "sleep_clk",
+};
+
+static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 2 },
+ { P_SLEEP_CLK, 6 },
+};
+
+static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll6",
+ "gpll0",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL6, 1 },
+ { P_GPLL0, 3 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
+ "xo",
+ "gpll0_out_main_div2",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0_DIV2, 2 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
+ "usb3phy_0_cc_pipe_clk",
+ "xo",
+};
+
+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
+ { P_USB3PHY_0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
+ "usb3phy_1_cc_pipe_clk",
+ "xo",
+};
+
+static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
+ { P_USB3PHY_1_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
+ "pcie20_phy0_pipe_clk",
+ "xo",
+};
+
+static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
+ { P_PCIE20_PHY0_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
+ "pcie20_phy1_pipe_clk",
+ "xo",
+};
+
+static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
+ { P_PCIE20_PHY1_PIPE, 0 },
+ { P_XO, 2 },
+};
+
+static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll6",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL6, 2 },
+ { P_GPLL0_DIV2, 4 },
+};
+
+static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0",
+ "gpll6",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL6, 2 },
+ { P_GPLL0_DIV2, 3 },
+};
+
+static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
+ "xo",
+ "bias_pll_nss_noc_clk",
+ "gpll0",
+ "gpll2",
+};
+
+static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL_NSS_NOC, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL2, 3 },
+};
+
+static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
+ "xo",
+ "nss_crypto_pll",
+ "gpll0",
+};
+
+static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_NSS_CRYPTO_PLL, 1 },
+ { P_GPLL0, 2 },
+};
+
+static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
+ "xo",
+ "ubi32_pll",
+ "gpll0",
+ "gpll2",
+ "gpll4",
+ "gpll6",
+};
+
+static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
+ { P_XO, 0 },
+ { P_UBI32_PLL, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL2, 3 },
+ { P_GPLL4, 4 },
+ { P_GPLL6, 5 },
+};
+
+static const char * const gcc_xo_gpll0_out_main_div2[] = {
+ "xo",
+ "gpll0_out_main_div2",
+};
+
+static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0_DIV2, 1 },
+};
+
+static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ "xo",
+ "bias_pll_cc_clk",
+ "gpll0",
+ "gpll4",
+ "nss_crypto_pll",
+ "ubi32_pll",
+};
+
+static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
+ { P_XO, 0 },
+ { P_BIAS_PLL, 1 },
+ { P_GPLL0, 2 },
+ { P_GPLL4, 3 },
+ { P_NSS_CRYPTO_PLL, 4 },
+ { P_UBI32_PLL, 5 },
+};
+
+static const char * const gcc_xo_gpll0_gpll4[] = {
+ "xo",
+ "gpll0",
+ "gpll4",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 2 },
+};
+
+static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_rx_clk",
+ "uniphy0_gcc_tx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_tx_clk",
+ "uniphy0_gcc_rx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_TX, 1 },
+ { P_UNIPHY0_RX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_rx_clk",
+ "uniphy0_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_RX, 1 },
+ { P_UNIPHY0_TX, 2 },
+ { P_UNIPHY1_RX, 3 },
+ { P_UNIPHY1_TX, 4 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
+ "xo",
+ "uniphy0_gcc_tx_clk",
+ "uniphy0_gcc_rx_clk",
+ "uniphy1_gcc_tx_clk",
+ "uniphy1_gcc_rx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map
+gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY0_TX, 1 },
+ { P_UNIPHY0_RX, 2 },
+ { P_UNIPHY1_TX, 3 },
+ { P_UNIPHY1_RX, 4 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
+ "xo",
+ "uniphy2_gcc_rx_clk",
+ "uniphy2_gcc_tx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY2_RX, 1 },
+ { P_UNIPHY2_TX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
+ "xo",
+ "uniphy2_gcc_tx_clk",
+ "uniphy2_gcc_rx_clk",
+ "ubi32_pll",
+ "bias_pll_cc_clk",
+};
+
+static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
+ { P_XO, 0 },
+ { P_UNIPHY2_TX, 1 },
+ { P_UNIPHY2_RX, 2 },
+ { P_UBI32_PLL, 5 },
+ { P_BIAS_PLL, 6 },
+};
+
+static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
+ "xo",
+ "gpll0",
+ "gpll6",
+ "gpll0_out_main_div2",
+ "sleep_clk",
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL6, 2 },
+ { P_GPLL0_DIV2, 4 },
+ { P_SLEEP_CLK, 6 },
+};
+
static struct clk_alpha_pll gpll0_main = {
.offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x0b000,
.enable_mask = BIT(0),
@@ -82,13 +439,194 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x21000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_names = (const char *[]){
"gpll0_main"
},
.num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ops,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll2_main = {
+ .offset = 0x4a000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll2_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll2 = {
+ .offset = 0x4a000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll2",
+ .parent_names = (const char *[]){
+ "gpll2_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll gpll4_main = {
+ .offset = 0x24000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(5),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x24000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll4",
+ .parent_names = (const char *[]){
+ "gpll4_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll gpll6_main = {
+ .offset = 0x37000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(7),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll6_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll6 = {
+ .offset = 0x37000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll6",
+ .parent_names = (const char *[]){
+ "gpll6_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor gpll6_out_main_div2 = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll6_out_main_div2",
+ .parent_names = (const char *[]){
+ "gpll6_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll ubi32_pll_main = {
+ .offset = 0x25000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(6),
+ .hw.init = &(struct clk_init_data){
+ .name = "ubi32_pll_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv ubi32_pll = {
+ .offset = 0x25000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
+ .width = 2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ubi32_pll",
+ .parent_names = (const char *[]){
+ "ubi32_pll_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_alpha_pll nss_crypto_pll_main = {
+ .offset = 0x22000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x0b000,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_crypto_pll_main",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv nss_crypto_pll = {
+ .offset = 0x22000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .width = 4,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_crypto_pll",
+ .parent_names = (const char *[]){
+ "nss_crypto_pll_main"
+ },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
},
};
@@ -428,6 +966,1063 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
},
};
+static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pcie0_axi_clk_src = {
+ .cmd_rcgr = 0x75054,
+ .freq_tbl = ftbl_pcie_axi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie0_axi_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+};
+
+static struct clk_rcg2 pcie0_aux_clk_src = {
+ .cmd_rcgr = 0x75024,
+ .freq_tbl = ftbl_pcie_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie0_aux_clk_src",
+ .parent_names = gcc_xo_gpll0_sleep_clk,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux pcie0_pipe_clk_src = {
+ .reg = 0x7501c,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie0_pipe_clk_src",
+ .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
+ .num_parents = 2,
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 pcie1_axi_clk_src = {
+ .cmd_rcgr = 0x76054,
+ .freq_tbl = ftbl_pcie_axi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie1_axi_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 pcie1_aux_clk_src = {
+ .cmd_rcgr = 0x76024,
+ .freq_tbl = ftbl_pcie_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie1_aux_clk_src",
+ .parent_names = gcc_xo_gpll0_sleep_clk,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux pcie1_pipe_clk_src = {
+ .reg = 0x7601c,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "pcie1_pipe_clk_src",
+ .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
+ .num_parents = 2,
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(24000000, P_GPLL2, 12, 1, 4),
+ F(48000000, P_GPLL2, 12, 1, 2),
+ F(96000000, P_GPLL2, 12, 0, 0),
+ F(177777778, P_GPLL0, 4.5, 0, 0),
+ F(192000000, P_GPLL2, 6, 0, 0),
+ F(384000000, P_GPLL2, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x42004,
+ .freq_tbl = ftbl_sdcc_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(160000000, P_GPLL0, 5, 0, 0),
+ F(308570000, P_GPLL6, 3.5, 0, 0),
+};
+
+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x5d000,
+ .freq_tbl = ftbl_sdcc_ice_core_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_ice_core_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+ .cmd_rcgr = 0x43004,
+ .freq_tbl = ftbl_sdcc_apps_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc2_apps_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb_master_clk_src[] = {
+ F(80000000, P_GPLL0_DIV2, 5, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ F(133330000, P_GPLL0, 6, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb0_master_clk_src = {
+ .cmd_rcgr = 0x3e00c,
+ .freq_tbl = ftbl_usb_master_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb0_master_clk_src",
+ .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb0_aux_clk_src = {
+ .cmd_rcgr = 0x3e05c,
+ .freq_tbl = ftbl_usb_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb0_aux_clk_src",
+ .parent_names = gcc_xo_gpll0_sleep_clk,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(20000000, P_GPLL6, 6, 1, 9),
+ F(60000000, P_GPLL6, 6, 1, 3),
+ { }
+};
+
+static struct clk_rcg2 usb0_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x3e020,
+ .freq_tbl = ftbl_usb_mock_utmi_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb0_mock_utmi_clk_src",
+ .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux usb0_pipe_clk_src = {
+ .reg = 0x3e048,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "usb0_pipe_clk_src",
+ .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
+ .num_parents = 2,
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 usb1_master_clk_src = {
+ .cmd_rcgr = 0x3f00c,
+ .freq_tbl = ftbl_usb_master_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb1_master_clk_src",
+ .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 usb1_aux_clk_src = {
+ .cmd_rcgr = 0x3f05c,
+ .freq_tbl = ftbl_usb_aux_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb1_aux_clk_src",
+ .parent_names = gcc_xo_gpll0_sleep_clk,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 usb1_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x3f020,
+ .freq_tbl = ftbl_usb_mock_utmi_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb1_mock_utmi_clk_src",
+ .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_mux usb1_pipe_clk_src = {
+ .reg = 0x3f048,
+ .shift = 8,
+ .width = 2,
+ .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "usb1_pipe_clk_src",
+ .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
+ .num_parents = 2,
+ .ops = &clk_regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_branch gcc_xo_clk_src = {
+ .halt_reg = 0x30018,
+ .clkr = {
+ .enable_reg = 0x30018,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_xo_clk_src",
+ .parent_names = (const char *[]){
+ "xo"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gcc_xo_div4_clk_src = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_xo_div4_clk_src",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0_DIV2, 8, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ F(133333333, P_GPLL0, 6, 0, 0),
+ F(160000000, P_GPLL0, 5, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ F(266666667, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 system_noc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x26004,
+ .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "system_noc_bfdcd_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+};
+
+static struct clk_fixed_factor system_noc_clk_src = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "system_noc_clk_src",
+ .parent_names = (const char *[]){
+ "system_noc_bfdcd_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(200000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_ce_clk_src = {
+ .cmd_rcgr = 0x68098,
+ .freq_tbl = ftbl_nss_ce_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ce_clk_src",
+ .parent_names = gcc_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
+ .cmd_rcgr = 0x68088,
+ .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_noc_bfdcd_clk_src",
+ .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor nss_noc_clk_src = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_noc_clk_src",
+ .parent_names = (const char *[]){
+ "nss_noc_bfdcd_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_crypto_clk_src = {
+ .cmd_rcgr = 0x68144,
+ .freq_tbl = ftbl_nss_crypto_clk_src,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_crypto_clk_src",
+ .parent_names = gcc_xo_nss_crypto_pll_gpll0,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(187200000, P_UBI32_PLL, 8, 0, 0),
+ F(748800000, P_UBI32_PLL, 2, 0, 0),
+ F(1497600000, P_UBI32_PLL, 1, 0, 0),
+ F(1689600000, P_UBI32_PLL, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_ubi0_clk_src = {
+ .cmd_rcgr = 0x68104,
+ .freq_tbl = ftbl_nss_ubi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ubi0_clk_src",
+ .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap_div nss_ubi0_div_clk_src = {
+ .reg = 0x68118,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_ubi0_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_ubi0_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_ubi1_clk_src = {
+ .cmd_rcgr = 0x68124,
+ .freq_tbl = ftbl_nss_ubi_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ubi1_clk_src",
+ .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap_div nss_ubi1_div_clk_src = {
+ .reg = 0x68138,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_ubi1_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_ubi1_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ro_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0_DIV2, 16, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ubi_mpt_clk_src = {
+ .cmd_rcgr = 0x68090,
+ .freq_tbl = ftbl_ubi_mpt_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ubi_mpt_clk_src",
+ .parent_names = gcc_xo_gpll0_out_main_div2,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(400000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_imem_clk_src = {
+ .cmd_rcgr = 0x68158,
+ .freq_tbl = ftbl_nss_imem_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll4_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_imem_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll4,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(300000000, P_BIAS_PLL, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_ppe_clk_src = {
+ .cmd_rcgr = 0x68080,
+ .freq_tbl = ftbl_nss_ppe_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_ppe_clk_src",
+ .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_ppe_cdiv_clk_src",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY0_RX, 5, 0, 0),
+ F(125000000, P_UNIPHY0_RX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port1_rx_clk_src = {
+ .cmd_rcgr = 0x68020,
+ .freq_tbl = ftbl_nss_port1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port1_rx_clk_src",
+ .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port1_rx_div_clk_src = {
+ .reg = 0x68400,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port1_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port1_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY0_TX, 5, 0, 0),
+ F(125000000, P_UNIPHY0_TX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port1_tx_clk_src = {
+ .cmd_rcgr = 0x68028,
+ .freq_tbl = ftbl_nss_port1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port1_tx_clk_src",
+ .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port1_tx_div_clk_src = {
+ .reg = 0x68404,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port1_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port1_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port2_rx_clk_src = {
+ .cmd_rcgr = 0x68030,
+ .freq_tbl = ftbl_nss_port1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port2_rx_clk_src",
+ .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port2_rx_div_clk_src = {
+ .reg = 0x68410,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port2_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port2_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port2_tx_clk_src = {
+ .cmd_rcgr = 0x68038,
+ .freq_tbl = ftbl_nss_port1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port2_tx_clk_src",
+ .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port2_tx_div_clk_src = {
+ .reg = 0x68414,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port2_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port2_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port3_rx_clk_src = {
+ .cmd_rcgr = 0x68040,
+ .freq_tbl = ftbl_nss_port1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port3_rx_clk_src",
+ .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port3_rx_div_clk_src = {
+ .reg = 0x68420,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port3_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port3_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port3_tx_clk_src = {
+ .cmd_rcgr = 0x68048,
+ .freq_tbl = ftbl_nss_port1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port3_tx_clk_src",
+ .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port3_tx_div_clk_src = {
+ .reg = 0x68424,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port3_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port3_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port4_rx_clk_src = {
+ .cmd_rcgr = 0x68050,
+ .freq_tbl = ftbl_nss_port1_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port4_rx_clk_src",
+ .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port4_rx_div_clk_src = {
+ .reg = 0x68430,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port4_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port4_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct clk_rcg2 nss_port4_tx_clk_src = {
+ .cmd_rcgr = 0x68058,
+ .freq_tbl = ftbl_nss_port1_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port4_tx_clk_src",
+ .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port4_tx_div_clk_src = {
+ .reg = 0x68434,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port4_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port4_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
+ F(78125000, P_UNIPHY1_RX, 4, 0, 0),
+ F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
+ F(156250000, P_UNIPHY1_RX, 2, 0, 0),
+ F(312500000, P_UNIPHY1_RX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port5_rx_clk_src = {
+ .cmd_rcgr = 0x68060,
+ .freq_tbl = ftbl_nss_port5_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port5_rx_clk_src",
+ .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
+ .num_parents = 7,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port5_rx_div_clk_src = {
+ .reg = 0x68440,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port5_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port5_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
+ F(78125000, P_UNIPHY1_TX, 4, 0, 0),
+ F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
+ F(156250000, P_UNIPHY1_TX, 2, 0, 0),
+ F(312500000, P_UNIPHY1_TX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port5_tx_clk_src = {
+ .cmd_rcgr = 0x68068,
+ .freq_tbl = ftbl_nss_port5_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port5_tx_clk_src",
+ .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
+ .num_parents = 7,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port5_tx_div_clk_src = {
+ .reg = 0x68444,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port5_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port5_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
+ F(78125000, P_UNIPHY2_RX, 4, 0, 0),
+ F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
+ F(156250000, P_UNIPHY2_RX, 2, 0, 0),
+ F(312500000, P_UNIPHY2_RX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port6_rx_clk_src = {
+ .cmd_rcgr = 0x68070,
+ .freq_tbl = ftbl_nss_port6_rx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port6_rx_clk_src",
+ .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port6_rx_div_clk_src = {
+ .reg = 0x68450,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port6_rx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port6_rx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
+ F(78125000, P_UNIPHY2_TX, 4, 0, 0),
+ F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
+ F(156250000, P_UNIPHY2_TX, 2, 0, 0),
+ F(312500000, P_UNIPHY2_TX, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 nss_port6_tx_clk_src = {
+ .cmd_rcgr = 0x68078,
+ .freq_tbl = ftbl_nss_port6_tx_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "nss_port6_tx_clk_src",
+ .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_regmap_div nss_port6_tx_div_clk_src = {
+ .reg = 0x68454,
+ .shift = 0,
+ .width = 4,
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "nss_port6_tx_div_clk_src",
+ .parent_names = (const char *[]){
+ "nss_port6_tx_clk_src"
+ },
+ .num_parents = 1,
+ .ops = &clk_regmap_div_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+ },
+};
+
+static struct freq_tbl ftbl_crypto_clk_src[] = {
+ F(40000000, P_GPLL0_DIV2, 10, 0, 0),
+ F(80000000, P_GPLL0, 10, 0, 0),
+ F(100000000, P_GPLL0, 8, 0, 0),
+ F(160000000, P_GPLL0, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 crypto_clk_src = {
+ .cmd_rcgr = 0x16004,
+ .freq_tbl = ftbl_crypto_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "crypto_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct freq_tbl ftbl_gp_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x08004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp1_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+ .cmd_rcgr = 0x09004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp2_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+ .cmd_rcgr = 0x0a004,
+ .freq_tbl = ftbl_gp_clk_src,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp3_clk_src",
+ .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
+ .num_parents = 5,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
static struct clk_branch gcc_blsp1_ahb_clk = {
.halt_reg = 0x01008,
.clkr = {
@@ -803,14 +2398,1957 @@ static struct clk_branch gcc_qpic_clk = {
},
};
+static struct clk_branch gcc_pcie0_ahb_clk = {
+ .halt_reg = 0x75010,
+ .clkr = {
+ .enable_reg = 0x75010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_aux_clk = {
+ .halt_reg = 0x75014,
+ .clkr = {
+ .enable_reg = 0x75014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_aux_clk",
+ .parent_names = (const char *[]){
+ "pcie0_aux_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_m_clk = {
+ .halt_reg = 0x75008,
+ .clkr = {
+ .enable_reg = 0x75008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_axi_m_clk",
+ .parent_names = (const char *[]){
+ "pcie0_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_clk = {
+ .halt_reg = 0x7500c,
+ .clkr = {
+ .enable_reg = 0x7500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_axi_s_clk",
+ .parent_names = (const char *[]){
+ "pcie0_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_pipe_clk = {
+ .halt_reg = 0x75018,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x75018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_pipe_clk",
+ .parent_names = (const char *[]){
+ "pcie0_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
+ .halt_reg = 0x26048,
+ .clkr = {
+ .enable_reg = 0x26048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_pcie0_axi_clk",
+ .parent_names = (const char *[]){
+ "pcie0_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_ahb_clk = {
+ .halt_reg = 0x76010,
+ .clkr = {
+ .enable_reg = 0x76010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_aux_clk = {
+ .halt_reg = 0x76014,
+ .clkr = {
+ .enable_reg = 0x76014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_aux_clk",
+ .parent_names = (const char *[]){
+ "pcie1_aux_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_m_clk = {
+ .halt_reg = 0x76008,
+ .clkr = {
+ .enable_reg = 0x76008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_axi_m_clk",
+ .parent_names = (const char *[]){
+ "pcie1_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_axi_s_clk = {
+ .halt_reg = 0x7600c,
+ .clkr = {
+ .enable_reg = 0x7600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_axi_s_clk",
+ .parent_names = (const char *[]){
+ "pcie1_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie1_pipe_clk = {
+ .halt_reg = 0x76018,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x76018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie1_pipe_clk",
+ .parent_names = (const char *[]){
+ "pcie1_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
+ .halt_reg = 0x2604c,
+ .clkr = {
+ .enable_reg = 0x2604c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_pcie1_axi_clk",
+ .parent_names = (const char *[]){
+ "pcie1_axi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_aux_clk = {
+ .halt_reg = 0x3e044,
+ .clkr = {
+ .enable_reg = 0x3e044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_aux_clk",
+ .parent_names = (const char *[]){
+ "usb0_aux_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
+ .halt_reg = 0x26040,
+ .clkr = {
+ .enable_reg = 0x26040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_usb0_axi_clk",
+ .parent_names = (const char *[]){
+ "usb0_master_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_master_clk = {
+ .halt_reg = 0x3e000,
+ .clkr = {
+ .enable_reg = 0x3e000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_master_clk",
+ .parent_names = (const char *[]){
+ "usb0_master_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_mock_utmi_clk = {
+ .halt_reg = 0x3e008,
+ .clkr = {
+ .enable_reg = 0x3e008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb0_mock_utmi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
+ .halt_reg = 0x3e080,
+ .clkr = {
+ .enable_reg = 0x3e080,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_phy_cfg_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_pipe_clk = {
+ .halt_reg = 0x3e040,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x3e040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_pipe_clk",
+ .parent_names = (const char *[]){
+ "usb0_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb0_sleep_clk = {
+ .halt_reg = 0x3e004,
+ .clkr = {
+ .enable_reg = 0x3e004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb0_sleep_clk",
+ .parent_names = (const char *[]){
+ "gcc_sleep_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_aux_clk = {
+ .halt_reg = 0x3f044,
+ .clkr = {
+ .enable_reg = 0x3f044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_aux_clk",
+ .parent_names = (const char *[]){
+ "usb1_aux_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
+ .halt_reg = 0x26044,
+ .clkr = {
+ .enable_reg = 0x26044,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sys_noc_usb1_axi_clk",
+ .parent_names = (const char *[]){
+ "usb1_master_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_master_clk = {
+ .halt_reg = 0x3f000,
+ .clkr = {
+ .enable_reg = 0x3f000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_master_clk",
+ .parent_names = (const char *[]){
+ "usb1_master_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_mock_utmi_clk = {
+ .halt_reg = 0x3f008,
+ .clkr = {
+ .enable_reg = 0x3f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb1_mock_utmi_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
+ .halt_reg = 0x3f080,
+ .clkr = {
+ .enable_reg = 0x3f080,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_phy_cfg_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_pipe_clk = {
+ .halt_reg = 0x3f040,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x3f040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_pipe_clk",
+ .parent_names = (const char *[]){
+ "usb1_pipe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb1_sleep_clk = {
+ .halt_reg = 0x3f004,
+ .clkr = {
+ .enable_reg = 0x3f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb1_sleep_clk",
+ .parent_names = (const char *[]){
+ "gcc_sleep_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x4201c,
+ .clkr = {
+ .enable_reg = 0x4201c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x42018,
+ .clkr = {
+ .enable_reg = 0x42018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+ .halt_reg = 0x5d014,
+ .clkr = {
+ .enable_reg = 0x5d014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ice_core_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_ice_core_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+ .halt_reg = 0x4301c,
+ .clkr = {
+ .enable_reg = 0x4301c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+ .halt_reg = 0x43018,
+ .clkr = {
+ .enable_reg = 0x43018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc2_apps_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mem_noc_nss_axi_clk = {
+ .halt_reg = 0x1d03c,
+ .clkr = {
+ .enable_reg = 0x1d03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mem_noc_nss_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ce_apb_clk = {
+ .halt_reg = 0x68174,
+ .clkr = {
+ .enable_reg = 0x68174,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ce_apb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ce_axi_clk = {
+ .halt_reg = 0x68170,
+ .clkr = {
+ .enable_reg = 0x68170,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ce_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_cfg_clk = {
+ .halt_reg = 0x68160,
+ .clkr = {
+ .enable_reg = 0x68160,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_cfg_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_crypto_clk = {
+ .halt_reg = 0x68164,
+ .clkr = {
+ .enable_reg = 0x68164,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_crypto_clk",
+ .parent_names = (const char *[]){
+ "nss_crypto_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_csr_clk = {
+ .halt_reg = 0x68318,
+ .clkr = {
+ .enable_reg = 0x68318,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_csr_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_edma_cfg_clk = {
+ .halt_reg = 0x6819c,
+ .clkr = {
+ .enable_reg = 0x6819c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_edma_cfg_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_edma_clk = {
+ .halt_reg = 0x68198,
+ .clkr = {
+ .enable_reg = 0x68198,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_edma_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_imem_clk = {
+ .halt_reg = 0x68178,
+ .clkr = {
+ .enable_reg = 0x68178,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_imem_clk",
+ .parent_names = (const char *[]){
+ "nss_imem_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_noc_clk = {
+ .halt_reg = 0x68168,
+ .clkr = {
+ .enable_reg = 0x68168,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_noc_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ppe_btq_clk = {
+ .halt_reg = 0x6833c,
+ .clkr = {
+ .enable_reg = 0x6833c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_btq_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ppe_cfg_clk = {
+ .halt_reg = 0x68194,
+ .clkr = {
+ .enable_reg = 0x68194,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_cfg_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ppe_clk = {
+ .halt_reg = 0x68190,
+ .clkr = {
+ .enable_reg = 0x68190,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ppe_ipe_clk = {
+ .halt_reg = 0x68338,
+ .clkr = {
+ .enable_reg = 0x68338,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ppe_ipe_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_ptp_ref_clk = {
+ .halt_reg = 0x6816c,
+ .clkr = {
+ .enable_reg = 0x6816c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_ptp_ref_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_cdiv_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ce_apb_clk = {
+ .halt_reg = 0x6830c,
+ .clkr = {
+ .enable_reg = 0x6830c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ce_apb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ce_axi_clk = {
+ .halt_reg = 0x68308,
+ .clkr = {
+ .enable_reg = 0x68308,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ce_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_crypto_clk = {
+ .halt_reg = 0x68314,
+ .clkr = {
+ .enable_reg = 0x68314,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_crypto_clk",
+ .parent_names = (const char *[]){
+ "nss_crypto_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
+ .halt_reg = 0x68304,
+ .clkr = {
+ .enable_reg = 0x68304,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ppe_cfg_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ppe_clk = {
+ .halt_reg = 0x68300,
+ .clkr = {
+ .enable_reg = 0x68300,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ppe_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
+ .halt_reg = 0x68180,
+ .clkr = {
+ .enable_reg = 0x68180,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_qosgen_ref_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_snoc_clk = {
+ .halt_reg = 0x68188,
+ .clkr = {
+ .enable_reg = 0x68188,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_snoc_clk",
+ .parent_names = (const char *[]){
+ "system_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
+ .halt_reg = 0x68184,
+ .clkr = {
+ .enable_reg = 0x68184,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_timeout_ref_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_div4_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
+ .halt_reg = 0x68270,
+ .clkr = {
+ .enable_reg = 0x68270,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ubi0_ahb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
+ .halt_reg = 0x68274,
+ .clkr = {
+ .enable_reg = 0x68274,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nssnoc_ubi1_ahb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_ahb_clk = {
+ .halt_reg = 0x6820c,
+ .clkr = {
+ .enable_reg = 0x6820c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_ahb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_axi_clk = {
+ .halt_reg = 0x68200,
+ .clkr = {
+ .enable_reg = 0x68200,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_nc_axi_clk = {
+ .halt_reg = 0x68204,
+ .clkr = {
+ .enable_reg = 0x68204,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_nc_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_core_clk = {
+ .halt_reg = 0x68210,
+ .clkr = {
+ .enable_reg = 0x68210,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_core_clk",
+ .parent_names = (const char *[]){
+ "nss_ubi0_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi0_mpt_clk = {
+ .halt_reg = 0x68208,
+ .clkr = {
+ .enable_reg = 0x68208,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi0_mpt_clk",
+ .parent_names = (const char *[]){
+ "ubi_mpt_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi1_ahb_clk = {
+ .halt_reg = 0x6822c,
+ .clkr = {
+ .enable_reg = 0x6822c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_ahb_clk",
+ .parent_names = (const char *[]){
+ "nss_ce_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi1_axi_clk = {
+ .halt_reg = 0x68220,
+ .clkr = {
+ .enable_reg = 0x68220,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi1_nc_axi_clk = {
+ .halt_reg = 0x68224,
+ .clkr = {
+ .enable_reg = 0x68224,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_nc_axi_clk",
+ .parent_names = (const char *[]){
+ "nss_noc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi1_core_clk = {
+ .halt_reg = 0x68230,
+ .clkr = {
+ .enable_reg = 0x68230,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_core_clk",
+ .parent_names = (const char *[]){
+ "nss_ubi1_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ubi1_mpt_clk = {
+ .halt_reg = 0x68228,
+ .clkr = {
+ .enable_reg = 0x68228,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ubi1_mpt_clk",
+ .parent_names = (const char *[]){
+ "ubi_mpt_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
+ .halt_reg = 0x56308,
+ .clkr = {
+ .enable_reg = 0x56308,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cmn_12gpll_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cmn_12gpll_sys_clk = {
+ .halt_reg = 0x5630c,
+ .clkr = {
+ .enable_reg = 0x5630c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cmn_12gpll_sys_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mdio_ahb_clk = {
+ .halt_reg = 0x58004,
+ .clkr = {
+ .enable_reg = 0x58004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mdio_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_ahb_clk = {
+ .halt_reg = 0x56008,
+ .clkr = {
+ .enable_reg = 0x56008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_sys_clk = {
+ .halt_reg = 0x5600c,
+ .clkr = {
+ .enable_reg = 0x5600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_sys_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_ahb_clk = {
+ .halt_reg = 0x56108,
+ .clkr = {
+ .enable_reg = 0x56108,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_sys_clk = {
+ .halt_reg = 0x5610c,
+ .clkr = {
+ .enable_reg = 0x5610c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_sys_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy2_ahb_clk = {
+ .halt_reg = 0x56208,
+ .clkr = {
+ .enable_reg = 0x56208,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy2_sys_clk = {
+ .halt_reg = 0x5620c,
+ .clkr = {
+ .enable_reg = 0x5620c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_sys_clk",
+ .parent_names = (const char *[]){
+ "gcc_xo_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port1_rx_clk = {
+ .halt_reg = 0x68240,
+ .clkr = {
+ .enable_reg = 0x68240,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port1_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port1_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port1_tx_clk = {
+ .halt_reg = 0x68244,
+ .clkr = {
+ .enable_reg = 0x68244,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port1_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port1_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port2_rx_clk = {
+ .halt_reg = 0x68248,
+ .clkr = {
+ .enable_reg = 0x68248,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port2_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port2_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port2_tx_clk = {
+ .halt_reg = 0x6824c,
+ .clkr = {
+ .enable_reg = 0x6824c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port2_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port2_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port3_rx_clk = {
+ .halt_reg = 0x68250,
+ .clkr = {
+ .enable_reg = 0x68250,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port3_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port3_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port3_tx_clk = {
+ .halt_reg = 0x68254,
+ .clkr = {
+ .enable_reg = 0x68254,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port3_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port3_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port4_rx_clk = {
+ .halt_reg = 0x68258,
+ .clkr = {
+ .enable_reg = 0x68258,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port4_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port4_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port4_tx_clk = {
+ .halt_reg = 0x6825c,
+ .clkr = {
+ .enable_reg = 0x6825c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port4_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port4_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port5_rx_clk = {
+ .halt_reg = 0x68260,
+ .clkr = {
+ .enable_reg = 0x68260,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port5_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port5_tx_clk = {
+ .halt_reg = 0x68264,
+ .clkr = {
+ .enable_reg = 0x68264,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port5_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port6_rx_clk = {
+ .halt_reg = 0x68268,
+ .clkr = {
+ .enable_reg = 0x68268,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port6_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port6_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_nss_port6_tx_clk = {
+ .halt_reg = 0x6826c,
+ .clkr = {
+ .enable_reg = 0x6826c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_nss_port6_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port6_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port1_mac_clk = {
+ .halt_reg = 0x68320,
+ .clkr = {
+ .enable_reg = 0x68320,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port1_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port2_mac_clk = {
+ .halt_reg = 0x68324,
+ .clkr = {
+ .enable_reg = 0x68324,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port2_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port3_mac_clk = {
+ .halt_reg = 0x68328,
+ .clkr = {
+ .enable_reg = 0x68328,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port3_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port4_mac_clk = {
+ .halt_reg = 0x6832c,
+ .clkr = {
+ .enable_reg = 0x6832c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port4_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port5_mac_clk = {
+ .halt_reg = 0x68330,
+ .clkr = {
+ .enable_reg = 0x68330,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port5_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_port6_mac_clk = {
+ .halt_reg = 0x68334,
+ .clkr = {
+ .enable_reg = 0x68334,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_port6_mac_clk",
+ .parent_names = (const char *[]){
+ "nss_ppe_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port1_rx_clk = {
+ .halt_reg = 0x56010,
+ .clkr = {
+ .enable_reg = 0x56010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port1_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port1_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port1_tx_clk = {
+ .halt_reg = 0x56014,
+ .clkr = {
+ .enable_reg = 0x56014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port1_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port1_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port2_rx_clk = {
+ .halt_reg = 0x56018,
+ .clkr = {
+ .enable_reg = 0x56018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port2_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port2_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port2_tx_clk = {
+ .halt_reg = 0x5601c,
+ .clkr = {
+ .enable_reg = 0x5601c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port2_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port2_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port3_rx_clk = {
+ .halt_reg = 0x56020,
+ .clkr = {
+ .enable_reg = 0x56020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port3_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port3_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port3_tx_clk = {
+ .halt_reg = 0x56024,
+ .clkr = {
+ .enable_reg = 0x56024,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port3_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port3_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port4_rx_clk = {
+ .halt_reg = 0x56028,
+ .clkr = {
+ .enable_reg = 0x56028,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port4_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port4_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port4_tx_clk = {
+ .halt_reg = 0x5602c,
+ .clkr = {
+ .enable_reg = 0x5602c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port4_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port4_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port5_rx_clk = {
+ .halt_reg = 0x56030,
+ .clkr = {
+ .enable_reg = 0x56030,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port5_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy0_port5_tx_clk = {
+ .halt_reg = 0x56034,
+ .clkr = {
+ .enable_reg = 0x56034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy0_port5_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_port5_rx_clk = {
+ .halt_reg = 0x56110,
+ .clkr = {
+ .enable_reg = 0x56110,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_port5_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy1_port5_tx_clk = {
+ .halt_reg = 0x56114,
+ .clkr = {
+ .enable_reg = 0x56114,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy1_port5_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port5_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy2_port6_rx_clk = {
+ .halt_reg = 0x56210,
+ .clkr = {
+ .enable_reg = 0x56210,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_port6_rx_clk",
+ .parent_names = (const char *[]){
+ "nss_port6_rx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_uniphy2_port6_tx_clk = {
+ .halt_reg = 0x56214,
+ .clkr = {
+ .enable_reg = 0x56214,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_uniphy2_port6_tx_clk",
+ .parent_names = (const char *[]){
+ "nss_port6_tx_div_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_ahb_clk = {
+ .halt_reg = 0x16024,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_ahb_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_axi_clk = {
+ .halt_reg = 0x16020,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_axi_clk",
+ .parent_names = (const char *[]){
+ "pcnoc_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_crypto_clk = {
+ .halt_reg = 0x1601c,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x0b004,
+ .enable_mask = BIT(2),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_crypto_clk",
+ .parent_names = (const char *[]){
+ "crypto_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x08000,
+ .clkr = {
+ .enable_reg = 0x08000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp1_clk",
+ .parent_names = (const char *[]){
+ "gp1_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x09000,
+ .clkr = {
+ .enable_reg = 0x09000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp2_clk",
+ .parent_names = (const char *[]){
+ "gp2_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x0a000,
+ .clkr = {
+ .enable_reg = 0x0a000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp3_clk",
+ .parent_names = (const char *[]){
+ "gp3_clk_src"
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_hw *gcc_ipq8074_hws[] = {
&gpll0_out_main_div2.hw,
+ &gpll6_out_main_div2.hw,
&pcnoc_clk_src.hw,
+ &system_noc_clk_src.hw,
+ &gcc_xo_div4_clk_src.hw,
+ &nss_noc_clk_src.hw,
+ &nss_ppe_cdiv_clk_src.hw,
};
static struct clk_regmap *gcc_ipq8074_clks[] = {
[GPLL0_MAIN] = &gpll0_main.clkr,
[GPLL0] = &gpll0.clkr,
+ [GPLL2_MAIN] = &gpll2_main.clkr,
+ [GPLL2] = &gpll2.clkr,
+ [GPLL4_MAIN] = &gpll4_main.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [GPLL6_MAIN] = &gpll6_main.clkr,
+ [GPLL6] = &gpll6.clkr,
+ [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
+ [UBI32_PLL] = &ubi32_pll.clkr,
+ [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
+ [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
@@ -831,6 +4369,63 @@ static struct clk_regmap *gcc_ipq8074_clks[] = {
[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
+ [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
+ [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
+ [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
+ [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
+ [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
+ [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
+ [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+ [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
+ [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
+ [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
+ [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
+ [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
+ [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
+ [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
+ [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
+ [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
+ [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
+ [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
+ [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
+ [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
+ [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
+ [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
+ [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
+ [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
+ [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
+ [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
+ [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
+ [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
+ [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
+ [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
+ [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
+ [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
+ [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
+ [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
+ [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
+ [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
+ [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
+ [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
+ [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
+ [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
+ [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
+ [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
+ [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
+ [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
+ [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
+ [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
+ [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
+ [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
+ [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
+ [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
+ [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
+ [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
@@ -853,6 +4448,119 @@ static struct clk_regmap *gcc_ipq8074_clks[] = {
[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
+ [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
+ [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
+ [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
+ [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
+ [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
+ [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
+ [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
+ [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
+ [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
+ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
+ [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
+ [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
+ [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
+ [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
+ [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
+ [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
+ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
+ [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
+ [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
+ [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
+ [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
+ [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
+ [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
+ [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
+ [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
+ [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
+ [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
+ [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
+ [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
+ [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
+ [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
+ [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
+ [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
+ [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
+ [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
+ [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
+ [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
+ [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
+ [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
+ [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
+ [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
+ [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
+ [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
+ [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
+ [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
+ [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
+ [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
+ [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
+ [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
+ [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
+ [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
+ [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
+ [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
+ [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
+ [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
+ [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
+ [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
+ [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
+ [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
+ [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
+ [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
+ [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
+ [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
+ [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
+ [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
+ [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
+ [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
+ [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
+ [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
+ [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
+ [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
+ [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
+ [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
+ [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
+ [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
+ [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
+ [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
+ [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
+ [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
+ [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
+ [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
+ [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
+ [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
+ [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
+ [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
+ [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
+ [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
+ [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
+ [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
+ [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
+ [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
+ [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
+ [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
+ [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
+ [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
+ [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
+ [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
+ [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
+ [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
+ [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
+ [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
+ [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq8074_resets[] = {
@@ -945,6 +4653,48 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] = {
[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
[GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
[GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
+ [GCC_UBI0_AXI_ARES] = { 0x68010, 0 },
+ [GCC_UBI0_AHB_ARES] = { 0x68010, 1 },
+ [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },
+ [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
+ [GCC_UBI0_CORE_CLAMP_ENABLE] = { 0x68010, 4 },
+ [GCC_UBI0_CLKRST_CLAMP_ENABLE] = { 0x68010, 5 },
+ [GCC_UBI1_AXI_ARES] = { 0x68010, 8 },
+ [GCC_UBI1_AHB_ARES] = { 0x68010, 9 },
+ [GCC_UBI1_NC_AXI_ARES] = { 0x68010, 10 },
+ [GCC_UBI1_DBG_ARES] = { 0x68010, 11 },
+ [GCC_UBI1_CORE_CLAMP_ENABLE] = { 0x68010, 12 },
+ [GCC_UBI1_CLKRST_CLAMP_ENABLE] = { 0x68010, 13 },
+ [GCC_NSS_CFG_ARES] = { 0x68010, 16 },
+ [GCC_NSS_IMEM_ARES] = { 0x68010, 17 },
+ [GCC_NSS_NOC_ARES] = { 0x68010, 18 },
+ [GCC_NSS_CRYPTO_ARES] = { 0x68010, 19 },
+ [GCC_NSS_CSR_ARES] = { 0x68010, 20 },
+ [GCC_NSS_CE_APB_ARES] = { 0x68010, 21 },
+ [GCC_NSS_CE_AXI_ARES] = { 0x68010, 22 },
+ [GCC_NSSNOC_CE_APB_ARES] = { 0x68010, 23 },
+ [GCC_NSSNOC_CE_AXI_ARES] = { 0x68010, 24 },
+ [GCC_NSSNOC_UBI0_AHB_ARES] = { 0x68010, 25 },
+ [GCC_NSSNOC_UBI1_AHB_ARES] = { 0x68010, 26 },
+ [GCC_NSSNOC_SNOC_ARES] = { 0x68010, 27 },
+ [GCC_NSSNOC_CRYPTO_ARES] = { 0x68010, 28 },
+ [GCC_NSSNOC_ATB_ARES] = { 0x68010, 29 },
+ [GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x68010, 30 },
+ [GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x68010, 31 },
+ [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },
+ [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },
+ [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },
+ [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },
+ [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
+ [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
+ [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
+ [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
+ [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
+ [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
+ [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },
+ [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },
+ [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },
+ [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
};
static const struct of_device_id gcc_ipq8074_match_table[] = {
diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 3410ee6..d6c7f50 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -1259,20 +1259,25 @@ static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
};
static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
+ F(128000, P_XO, 10, 1, 15),
F(256000, P_XO, 5, 1, 15),
+ F(384000, P_XO, 5, 1, 10),
F(512000, P_XO, 5, 2, 15),
+ F(576000, P_XO, 5, 3, 20),
F(705600, P_GPLL1, 16, 1, 80),
F(768000, P_XO, 5, 1, 5),
F(800000, P_XO, 5, 5, 24),
- F(1024000, P_GPLL1, 14, 1, 63),
+ F(1024000, P_XO, 5, 4, 15),
F(1152000, P_XO, 1, 3, 50),
F(1411200, P_GPLL1, 16, 1, 40),
F(1536000, P_XO, 1, 2, 25),
F(1600000, P_XO, 12, 0, 0),
- F(2048000, P_GPLL1, 9, 1, 49),
+ F(1728000, P_XO, 5, 9, 20),
+ F(2048000, P_XO, 5, 8, 15),
+ F(2304000, P_XO, 5, 3, 5),
F(2400000, P_XO, 8, 0, 0),
F(2822400, P_GPLL1, 16, 1, 20),
- F(3072000, P_GPLL1, 14, 1, 21),
+ F(3072000, P_XO, 5, 4, 5),
F(4096000, P_GPLL1, 9, 2, 49),
F(4800000, P_XO, 4, 0, 0),
F(5644800, P_GPLL1, 16, 1, 10),
@@ -1431,6 +1436,7 @@ static struct clk_branch gcc_ultaudio_stc_xo_clk = {
static const struct freq_tbl ftbl_codec_clk[] = {
F(9600000, P_XO, 2, 0, 0),
+ F(12288000, P_XO, 1, 16, 25),
F(19200000, P_XO, 1, 0, 0),
F(11289600, P_EXT_MCLK, 1, 0, 0),
{ }
@@ -1438,6 +1444,7 @@ static const struct freq_tbl ftbl_codec_clk[] = {
static struct clk_rcg2 codec_digcodec_clk_src = {
.cmd_rcgr = 0x1c09c,
+ .mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_xo_gpll1_emclk_sleep_map,
.freq_tbl = ftbl_codec_clk,
diff --git a/drivers/clk/qcom/gcc-msm8994.c b/drivers/clk/qcom/gcc-msm8994.c
index 7983288..1e38efc 100644
--- a/drivers/clk/qcom/gcc-msm8994.c
+++ b/drivers/clk/qcom/gcc-msm8994.c
@@ -73,6 +73,7 @@ static struct clk_fixed_factor xo = {
static struct clk_alpha_pll gpll0_early = {
.offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x1480,
.enable_mask = BIT(0),
@@ -88,6 +89,7 @@ static struct clk_alpha_pll gpll0_early = {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data)
{
.name = "gpll0",
@@ -99,6 +101,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
static struct clk_alpha_pll gpll4_early = {
.offset = 0x1dc0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x1480,
.enable_mask = BIT(4),
@@ -114,6 +117,7 @@ static struct clk_alpha_pll gpll4_early = {
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x1dc0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data)
{
.name = "gpll4",
diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 7ddec88..5d74512 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -227,6 +227,7 @@ static struct clk_fixed_factor xo = {
static struct clk_alpha_pll gpll0_early = {
.offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(0),
@@ -252,6 +253,7 @@ static struct clk_fixed_factor gpll0_early_div = {
static struct clk_alpha_pll_postdiv gpll0 = {
.offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll0",
.parent_names = (const char *[]){ "gpll0_early" },
@@ -262,6 +264,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
static struct clk_alpha_pll gpll4_early = {
.offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(4),
@@ -276,6 +279,7 @@ static struct clk_alpha_pll gpll4_early = {
static struct clk_alpha_pll_postdiv gpll4 = {
.offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.clkr.hw.init = &(struct clk_init_data){
.name = "gpll4",
.parent_names = (const char *[]){ "gpll4_early" },
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 352394d..66a2fa4 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -267,6 +267,7 @@ static struct pll_vco mmpll_t_vco[] = {
static struct clk_alpha_pll mmpll0_early = {
.offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr = {
@@ -283,6 +284,7 @@ static struct clk_alpha_pll mmpll0_early = {
static struct clk_alpha_pll_postdiv mmpll0 = {
.offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll0",
@@ -295,6 +297,7 @@ static struct clk_alpha_pll_postdiv mmpll0 = {
static struct clk_alpha_pll mmpll1_early = {
.offset = 0x30,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr = {
@@ -311,6 +314,7 @@ static struct clk_alpha_pll mmpll1_early = {
static struct clk_alpha_pll_postdiv mmpll1 = {
.offset = 0x30,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll1",
@@ -323,6 +327,7 @@ static struct clk_alpha_pll_postdiv mmpll1 = {
static struct clk_alpha_pll mmpll2_early = {
.offset = 0x4100,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_gfx_vco,
.num_vco = ARRAY_SIZE(mmpll_gfx_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -335,6 +340,7 @@ static struct clk_alpha_pll mmpll2_early = {
static struct clk_alpha_pll_postdiv mmpll2 = {
.offset = 0x4100,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll2",
@@ -347,6 +353,7 @@ static struct clk_alpha_pll_postdiv mmpll2 = {
static struct clk_alpha_pll mmpll3_early = {
.offset = 0x60,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -359,6 +366,7 @@ static struct clk_alpha_pll mmpll3_early = {
static struct clk_alpha_pll_postdiv mmpll3 = {
.offset = 0x60,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll3",
@@ -371,6 +379,7 @@ static struct clk_alpha_pll_postdiv mmpll3 = {
static struct clk_alpha_pll mmpll4_early = {
.offset = 0x90,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_t_vco,
.num_vco = ARRAY_SIZE(mmpll_t_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -383,6 +392,7 @@ static struct clk_alpha_pll mmpll4_early = {
static struct clk_alpha_pll_postdiv mmpll4 = {
.offset = 0x90,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll4",
@@ -395,6 +405,7 @@ static struct clk_alpha_pll_postdiv mmpll4 = {
static struct clk_alpha_pll mmpll5_early = {
.offset = 0xc0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_p_vco,
.num_vco = ARRAY_SIZE(mmpll_p_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -407,6 +418,7 @@ static struct clk_alpha_pll mmpll5_early = {
static struct clk_alpha_pll_postdiv mmpll5 = {
.offset = 0xc0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll5",
@@ -419,6 +431,7 @@ static struct clk_alpha_pll_postdiv mmpll5 = {
static struct clk_alpha_pll mmpll8_early = {
.offset = 0x4130,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_gfx_vco,
.num_vco = ARRAY_SIZE(mmpll_gfx_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -431,6 +444,7 @@ static struct clk_alpha_pll mmpll8_early = {
static struct clk_alpha_pll_postdiv mmpll8 = {
.offset = 0x4130,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 4,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll8",
@@ -443,6 +457,7 @@ static struct clk_alpha_pll_postdiv mmpll8 = {
static struct clk_alpha_pll mmpll9_early = {
.offset = 0x4200,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.vco_table = mmpll_t_vco,
.num_vco = ARRAY_SIZE(mmpll_t_vco),
.clkr.hw.init = &(struct clk_init_data){
@@ -455,6 +470,7 @@ static struct clk_alpha_pll mmpll9_early = {
static struct clk_alpha_pll_postdiv mmpll9 = {
.offset = 0x4200,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
.width = 2,
.clkr.hw.init = &(struct clk_init_data){
.name = "mmpll9",
diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c
index 229c96d..f5be022 100644
--- a/drivers/clk/spear/clk-frac-synth.c
+++ b/drivers/clk/spear/clk-frac-synth.c
@@ -131,7 +131,7 @@ struct clk *clk_register_frac(const char *name, const char *parent_name,
struct clk *clk;
if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
- pr_err("Invalid arguments passed");
+ pr_err("Invalid arguments passed\n");
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c
index 28262f4..6ed406d 100644
--- a/drivers/clk/spear/clk-gpt-synth.c
+++ b/drivers/clk/spear/clk-gpt-synth.c
@@ -120,7 +120,7 @@ struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
struct clk *clk;
if (!name || !parent_name || !reg || !rtbl || !rtbl_cnt) {
- pr_err("Invalid arguments passed");
+ pr_err("Invalid arguments passed\n");
return ERR_PTR(-EINVAL);
}
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index a2293ee..5ab295d 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -19,10 +19,6 @@
clk-dra7-atl.o dpll3xxx.o dpll44xx.o
obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o
-ifdef CONFIG_ATAGS
-obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o
-endif
-
endif # CONFIG_ARCH_OMAP2PLUS
obj-$(CONFIG_COMMON_CLK_TI_ADPLL) += adpll.o
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 83b148f..9498e93 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -133,9 +133,10 @@ static const struct clk_ops apll_ck_ops = {
.get_parent = &dra7_init_apll_parent,
};
-static void __init omap_clk_register_apll(struct clk_hw *hw,
+static void __init omap_clk_register_apll(void *user,
struct device_node *node)
{
+ struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *ad = clk_hw->dpll_data;
struct clk *clk;
diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c
index 0e47d95..612491a 100644
--- a/drivers/clk/ti/clk-33xx.c
+++ b/drivers/clk/ti/clk-33xx.c
@@ -19,98 +19,201 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
+#include <dt-bindings/clock/am3.h>
#include "clock.h"
+static const char * const am3_gpio1_dbclk_parents[] __initconst = {
+ "l4_per_cm:clk:0138:0",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
+ { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
+ { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
+ { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
+ { AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
+ { AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP, "lcd_gclk", "lcdc_clkdm" },
+ { AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
+ { AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
+ { AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
+ { AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
+ { AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
+ { AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
+ { AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
+ { AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
+ { AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
+ { AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
+ { AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
+ { AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
+ { AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
+ { AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
+ { AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
+ { AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
+ { AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
+ { AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
+ { AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
+ { AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
+ { AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
+ { 0 },
+};
+
+static const char * const am3_gpio0_dbclk_parents[] __initconst = {
+ "gpio0_dbclk_mux_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
+ { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
+ "sys_clkin_ck",
+ NULL,
+};
+
+static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
+ "l4_wkup_cm:clk:0010:19",
+ "l4_wkup_cm:clk:0010:30",
+ NULL,
+};
+
+static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
+ "l4_wkup_cm:clk:0010:20",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
+ .max_div = 64,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
+ "l4_wkup_cm:clk:0010:22",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
+ .max_div = 64,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const char * const am3_dbg_clka_ck_parents[] __initconst = {
+ "dpll_core_m4_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
+ { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
+ { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
+ { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
+ { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
+ { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
+ { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
+ { AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
+ { AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
+ { AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
+ { AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
+ { AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
+ { AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
+ { AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
+ { AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
+ { AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
+ { AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
+ { AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
+ { AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
+ { AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
+ { AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
+ { AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
+ { AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
+ { 0x44e00014, am3_l4_per_clkctrl_regs },
+ { 0x44e00404, am3_l4_wkup_clkctrl_regs },
+ { 0x44e00604, am3_mpu_clkctrl_regs },
+ { 0x44e00800, am3_l4_rtc_clkctrl_regs },
+ { 0x44e00904, am3_gfx_l3_clkctrl_regs },
+ { 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk am33xx_clks[] = {
- DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
- DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
- DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
- DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
- DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_div2_ck", "dpll_ddr_m2_div2_ck"),
- DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
- DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
- DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
- DT_CLK(NULL, "cefuse_fck", "cefuse_fck"),
- DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
- DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
- DT_CLK("481cc000.d_can", NULL, "dcan0_fck"),
- DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
- DT_CLK("481d0000.d_can", NULL, "dcan1_fck"),
- DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
- DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
- DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
- DT_CLK(NULL, "mmu_fck", "mmu_fck"),
- DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
- DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
- DT_CLK(NULL, "sha0_fck", "sha0_fck"),
- DT_CLK(NULL, "aes0_fck", "aes0_fck"),
- DT_CLK(NULL, "rng_fck", "rng_fck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "usbotg_fck", "usbotg_fck"),
- DT_CLK(NULL, "ieee5000_fck", "ieee5000_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
- DT_CLK(NULL, "l4_rtc_gclk", "l4_rtc_gclk"),
- DT_CLK(NULL, "l3_gclk", "l3_gclk"),
- DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
- DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
- DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
- DT_CLK(NULL, "l4fw_gclk", "l4fw_gclk"),
- DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
- DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
- DT_CLK(NULL, "sysclk_div_ck", "sysclk_div_ck"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
- DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "lcd_gclk", "lcd_gclk"),
- DT_CLK(NULL, "mmc_clk", "mmc_clk"),
- DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
- DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
- DT_CLK(NULL, "sysclkout_pre_ck", "sysclkout_pre_ck"),
- DT_CLK(NULL, "clkout2_div_ck", "clkout2_div_ck"),
- DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
+ DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "dbg_sysclk_ck", "dbg_sysclk_ck"),
- DT_CLK(NULL, "dbg_clka_ck", "dbg_clka_ck"),
- DT_CLK(NULL, "stm_pmd_clock_mux_ck", "stm_pmd_clock_mux_ck"),
- DT_CLK(NULL, "trace_pmd_clk_mux_ck", "trace_pmd_clk_mux_ck"),
- DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
- DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
- DT_CLK(NULL, "clkout2_ck", "clkout2_ck"),
- DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
- DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
- DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
- DT_CLK("48300200.pwm", "tbclk", "ehrpwm0_tbclk"),
- DT_CLK("48302200.pwm", "tbclk", "ehrpwm1_tbclk"),
- DT_CLK("48304200.pwm", "tbclk", "ehrpwm2_tbclk"),
+ DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
+ DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
+ DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
+ DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
+ DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
+ DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
+ DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
+ DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
+ DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
{ .node_name = NULL },
};
@@ -133,6 +236,8 @@ int __init am33xx_dt_clk_init(void)
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
+
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
diff --git a/drivers/clk/ti/clk-3xxx-legacy.c b/drivers/clk/ti/clk-3xxx-legacy.c
deleted file mode 100644
index 0fbf8a9..0000000
--- a/drivers/clk/ti/clk-3xxx-legacy.c
+++ /dev/null
@@ -1,4656 +0,0 @@
-/*
- * OMAP3 Legacy clock data
- *
- * Copyright (C) 2014 Texas Instruments, Inc
- * Tero Kristo (t-kristo@ti.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/ti.h>
-
-#include "clock.h"
-
-static struct ti_clk_fixed virt_12m_ck_data = {
- .frequency = 12000000,
-};
-
-static struct ti_clk virt_12m_ck = {
- .name = "virt_12m_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_12m_ck_data,
-};
-
-static struct ti_clk_fixed virt_13m_ck_data = {
- .frequency = 13000000,
-};
-
-static struct ti_clk virt_13m_ck = {
- .name = "virt_13m_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_13m_ck_data,
-};
-
-static struct ti_clk_fixed virt_19200000_ck_data = {
- .frequency = 19200000,
-};
-
-static struct ti_clk virt_19200000_ck = {
- .name = "virt_19200000_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_19200000_ck_data,
-};
-
-static struct ti_clk_fixed virt_26000000_ck_data = {
- .frequency = 26000000,
-};
-
-static struct ti_clk virt_26000000_ck = {
- .name = "virt_26000000_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_26000000_ck_data,
-};
-
-static struct ti_clk_fixed virt_38_4m_ck_data = {
- .frequency = 38400000,
-};
-
-static struct ti_clk virt_38_4m_ck = {
- .name = "virt_38_4m_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_38_4m_ck_data,
-};
-
-static struct ti_clk_fixed virt_16_8m_ck_data = {
- .frequency = 16800000,
-};
-
-static struct ti_clk virt_16_8m_ck = {
- .name = "virt_16_8m_ck",
- .type = TI_CLK_FIXED,
- .data = &virt_16_8m_ck_data,
-};
-
-static const char *osc_sys_ck_parents[] = {
- "virt_12m_ck",
- "virt_13m_ck",
- "virt_19200000_ck",
- "virt_26000000_ck",
- "virt_38_4m_ck",
- "virt_16_8m_ck",
-};
-
-static struct ti_clk_mux osc_sys_ck_data = {
- .num_parents = ARRAY_SIZE(osc_sys_ck_parents),
- .reg = 0xd40,
- .module = TI_CLKM_PRM,
- .parents = osc_sys_ck_parents,
-};
-
-static struct ti_clk osc_sys_ck = {
- .name = "osc_sys_ck",
- .type = TI_CLK_MUX,
- .data = &osc_sys_ck_data,
-};
-
-static struct ti_clk_divider sys_ck_data = {
- .parent = "osc_sys_ck",
- .bit_shift = 6,
- .max_div = 3,
- .reg = 0x1270,
- .module = TI_CLKM_PRM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk sys_ck = {
- .name = "sys_ck",
- .type = TI_CLK_DIVIDER,
- .data = &sys_ck_data,
-};
-
-static const char *dpll3_ck_parents[] = {
- "sys_ck",
- "sys_ck",
-};
-
-static struct ti_clk_dpll dpll3_ck_data = {
- .num_parents = ARRAY_SIZE(dpll3_ck_parents),
- .control_reg = 0xd00,
- .idlest_reg = 0xd20,
- .mult_div1_reg = 0xd40,
- .autoidle_reg = 0xd30,
- .module = TI_CLKM_CM,
- .parents = dpll3_ck_parents,
- .flags = CLKF_CORE,
- .freqsel_mask = 0xf0,
- .div1_mask = 0x7f00,
- .idlest_mask = 0x1,
- .auto_recal_bit = 0x3,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x5,
- .max_multiplier = 0x7ff,
- .enable_mask = 0x7,
- .mult_mask = 0x7ff0000,
- .recal_st_bit = 0x5,
- .autoidle_mask = 0x7,
-};
-
-static struct ti_clk dpll3_ck = {
- .name = "dpll3_ck",
- .clkdm_name = "dpll3_clkdm",
- .type = TI_CLK_DPLL,
- .data = &dpll3_ck_data,
-};
-
-static struct ti_clk_divider dpll3_m2_ck_data = {
- .parent = "dpll3_ck",
- .bit_shift = 27,
- .max_div = 31,
- .reg = 0xd40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll3_m2_ck = {
- .name = "dpll3_m2_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll3_m2_ck_data,
-};
-
-static struct ti_clk_fixed_factor core_ck_data = {
- .parent = "dpll3_m2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_ck = {
- .name = "core_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_ck_data,
-};
-
-static struct ti_clk_divider l3_ick_data = {
- .parent = "core_ck",
- .max_div = 3,
- .reg = 0xa40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk l3_ick = {
- .name = "l3_ick",
- .type = TI_CLK_DIVIDER,
- .data = &l3_ick_data,
-};
-
-static struct ti_clk_fixed_factor security_l3_ick_data = {
- .parent = "l3_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk security_l3_ick = {
- .name = "security_l3_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &security_l3_ick_data,
-};
-
-static struct ti_clk_fixed_factor wkup_l4_ick_data = {
- .parent = "sys_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk wkup_l4_ick = {
- .name = "wkup_l4_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &wkup_l4_ick_data,
-};
-
-static struct ti_clk_gate usim_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 9,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk usim_ick = {
- .name = "usim_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &usim_ick_data,
-};
-
-static struct ti_clk_gate dss2_alwon_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 1,
- .reg = 0xe00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk dss2_alwon_fck = {
- .name = "dss2_alwon_fck",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss2_alwon_fck_data,
-};
-
-static struct ti_clk_divider l4_ick_data = {
- .parent = "l3_ick",
- .bit_shift = 2,
- .max_div = 3,
- .reg = 0xa40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk l4_ick = {
- .name = "l4_ick",
- .type = TI_CLK_DIVIDER,
- .data = &l4_ick_data,
-};
-
-static struct ti_clk_fixed_factor core_l4_ick_data = {
- .parent = "l4_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_l4_ick = {
- .name = "core_l4_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_l4_ick_data,
-};
-
-static struct ti_clk_gate mmchs2_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 25,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mmchs2_ick = {
- .name = "mmchs2_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs2_ick_data,
-};
-
-static const char *dpll4_ck_parents[] = {
- "sys_ck",
- "sys_ck",
-};
-
-static struct ti_clk_dpll dpll4_ck_data = {
- .num_parents = ARRAY_SIZE(dpll4_ck_parents),
- .control_reg = 0xd00,
- .idlest_reg = 0xd20,
- .mult_div1_reg = 0xd44,
- .autoidle_reg = 0xd30,
- .module = TI_CLKM_CM,
- .parents = dpll4_ck_parents,
- .flags = CLKF_PER,
- .freqsel_mask = 0xf00000,
- .modes = 0x82,
- .div1_mask = 0x7f,
- .idlest_mask = 0x2,
- .auto_recal_bit = 0x13,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x6,
- .max_multiplier = 0x7ff,
- .enable_mask = 0x70000,
- .mult_mask = 0x7ff00,
- .recal_st_bit = 0x6,
- .autoidle_mask = 0x38,
-};
-
-static struct ti_clk dpll4_ck = {
- .name = "dpll4_ck",
- .clkdm_name = "dpll4_clkdm",
- .type = TI_CLK_DPLL,
- .data = &dpll4_ck_data,
-};
-
-static struct ti_clk_divider dpll4_m2_ck_data = {
- .parent = "dpll4_ck",
- .max_div = 63,
- .reg = 0xd48,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll4_m2_ck = {
- .name = "dpll4_m2_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll4_m2_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll4_m2x2_mul_ck_data = {
- .parent = "dpll4_m2_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll4_m2x2_mul_ck = {
- .name = "dpll4_m2x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_m2x2_mul_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m2x2_ck_data = {
- .parent = "dpll4_m2x2_mul_ck",
- .bit_shift = 0x1b,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m2x2_ck = {
- .name = "dpll4_m2x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m2x2_ck_data,
-};
-
-static struct ti_clk_fixed_factor omap_96m_alwon_fck_data = {
- .parent = "dpll4_m2x2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk omap_96m_alwon_fck = {
- .name = "omap_96m_alwon_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_96m_alwon_fck_data,
-};
-
-static struct ti_clk_fixed_factor cm_96m_fck_data = {
- .parent = "omap_96m_alwon_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk cm_96m_fck = {
- .name = "cm_96m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &cm_96m_fck_data,
-};
-
-static const char *omap_96m_fck_parents[] = {
- "cm_96m_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux omap_96m_fck_data = {
- .bit_shift = 6,
- .num_parents = ARRAY_SIZE(omap_96m_fck_parents),
- .reg = 0xd40,
- .module = TI_CLKM_CM,
- .parents = omap_96m_fck_parents,
-};
-
-static struct ti_clk omap_96m_fck = {
- .name = "omap_96m_fck",
- .type = TI_CLK_MUX,
- .data = &omap_96m_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_96m_fck_data = {
- .parent = "omap_96m_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_96m_fck = {
- .name = "core_96m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_96m_fck_data,
-};
-
-static struct ti_clk_gate mspro_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 23,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mspro_fck = {
- .name = "mspro_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mspro_fck_data,
-};
-
-static struct ti_clk_gate dss_ick_3430es2_data = {
- .parent = "l4_ick",
- .bit_shift = 0,
- .reg = 0xe10,
- .module = TI_CLKM_CM,
- .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk dss_ick_3430es2 = {
- .name = "dss_ick",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss_ick_3430es2_data,
-};
-
-static struct ti_clk_gate uart4_ick_am35xx_data = {
- .parent = "core_l4_ick",
- .bit_shift = 23,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk uart4_ick_am35xx = {
- .name = "uart4_ick_am35xx",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart4_ick_am35xx_data,
-};
-
-static struct ti_clk_fixed_factor security_l4_ick2_data = {
- .parent = "l4_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk security_l4_ick2 = {
- .name = "security_l4_ick2",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &security_l4_ick2_data,
-};
-
-static struct ti_clk_gate aes1_ick_data = {
- .parent = "security_l4_ick2",
- .bit_shift = 3,
- .reg = 0xa14,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk aes1_ick = {
- .name = "aes1_ick",
- .type = TI_CLK_GATE,
- .data = &aes1_ick_data,
-};
-
-static const char *dpll5_ck_parents[] = {
- "sys_ck",
- "sys_ck",
-};
-
-static struct ti_clk_dpll dpll5_ck_data = {
- .num_parents = ARRAY_SIZE(dpll5_ck_parents),
- .control_reg = 0xd04,
- .idlest_reg = 0xd24,
- .mult_div1_reg = 0xd4c,
- .autoidle_reg = 0xd34,
- .module = TI_CLKM_CM,
- .parents = dpll5_ck_parents,
- .freqsel_mask = 0xf0,
- .modes = 0x82,
- .div1_mask = 0x7f,
- .idlest_mask = 0x1,
- .auto_recal_bit = 0x3,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x19,
- .max_multiplier = 0x7ff,
- .enable_mask = 0x7,
- .mult_mask = 0x7ff00,
- .recal_st_bit = 0x19,
- .autoidle_mask = 0x7,
-};
-
-static struct ti_clk dpll5_ck = {
- .name = "dpll5_ck",
- .clkdm_name = "dpll5_clkdm",
- .type = TI_CLK_DPLL,
- .data = &dpll5_ck_data,
-};
-
-static struct ti_clk_divider dpll5_m2_ck_data = {
- .parent = "dpll5_ck",
- .max_div = 31,
- .reg = 0xd50,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll5_m2_ck = {
- .name = "dpll5_m2_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll5_m2_ck_data,
-};
-
-static struct ti_clk_gate usbhost_120m_fck_data = {
- .parent = "dpll5_m2_ck",
- .bit_shift = 1,
- .reg = 0x1400,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk usbhost_120m_fck = {
- .name = "usbhost_120m_fck",
- .clkdm_name = "usbhost_clkdm",
- .type = TI_CLK_GATE,
- .data = &usbhost_120m_fck_data,
-};
-
-static struct ti_clk_fixed_factor cm_96m_d2_fck_data = {
- .parent = "cm_96m_fck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk cm_96m_d2_fck = {
- .name = "cm_96m_d2_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &cm_96m_d2_fck_data,
-};
-
-static struct ti_clk_fixed sys_altclk_data = {
- .frequency = 0x0,
-};
-
-static struct ti_clk sys_altclk = {
- .name = "sys_altclk",
- .type = TI_CLK_FIXED,
- .data = &sys_altclk_data,
-};
-
-static const char *omap_48m_fck_parents[] = {
- "cm_96m_d2_fck",
- "sys_altclk",
-};
-
-static struct ti_clk_mux omap_48m_fck_data = {
- .bit_shift = 3,
- .num_parents = ARRAY_SIZE(omap_48m_fck_parents),
- .reg = 0xd40,
- .module = TI_CLKM_CM,
- .parents = omap_48m_fck_parents,
-};
-
-static struct ti_clk omap_48m_fck = {
- .name = "omap_48m_fck",
- .type = TI_CLK_MUX,
- .data = &omap_48m_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_48m_fck_data = {
- .parent = "omap_48m_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_48m_fck = {
- .name = "core_48m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_48m_fck_data,
-};
-
-static struct ti_clk_fixed mcbsp_clks_data = {
- .frequency = 0x0,
-};
-
-static struct ti_clk mcbsp_clks = {
- .name = "mcbsp_clks",
- .type = TI_CLK_FIXED,
- .data = &mcbsp_clks_data,
-};
-
-static struct ti_clk_gate mcbsp2_gate_fck_data = {
- .parent = "mcbsp_clks",
- .bit_shift = 0,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_fixed_factor per_96m_fck_data = {
- .parent = "omap_96m_alwon_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk per_96m_fck = {
- .name = "per_96m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &per_96m_fck_data,
-};
-
-static const char *mcbsp2_mux_fck_parents[] = {
- "per_96m_fck",
- "mcbsp_clks",
-};
-
-static struct ti_clk_mux mcbsp2_mux_fck_data = {
- .bit_shift = 6,
- .num_parents = ARRAY_SIZE(mcbsp2_mux_fck_parents),
- .reg = 0x274,
- .module = TI_CLKM_SCRM,
- .parents = mcbsp2_mux_fck_parents,
-};
-
-static struct ti_clk_composite mcbsp2_fck_data = {
- .mux = &mcbsp2_mux_fck_data,
- .gate = &mcbsp2_gate_fck_data,
-};
-
-static struct ti_clk mcbsp2_fck = {
- .name = "mcbsp2_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &mcbsp2_fck_data,
-};
-
-static struct ti_clk_fixed_factor dpll3_m2x2_ck_data = {
- .parent = "dpll3_m2_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll3_m2x2_ck = {
- .name = "dpll3_m2x2_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll3_m2x2_ck_data,
-};
-
-static struct ti_clk_fixed_factor corex2_fck_data = {
- .parent = "dpll3_m2x2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk corex2_fck = {
- .name = "corex2_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &corex2_fck_data,
-};
-
-static struct ti_clk_gate ssi_ssr_gate_fck_3430es1_data = {
- .parent = "corex2_fck",
- .bit_shift = 0,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_NO_WAIT,
-};
-
-static int ssi_ssr_div_fck_3430es1_divs[] = {
- 0,
- 1,
- 2,
- 3,
- 4,
- 0,
- 6,
- 0,
- 8,
-};
-
-static struct ti_clk_divider ssi_ssr_div_fck_3430es1_data = {
- .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es1_divs),
- .parent = "corex2_fck",
- .bit_shift = 8,
- .dividers = ssi_ssr_div_fck_3430es1_divs,
- .reg = 0xa40,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_composite ssi_ssr_fck_3430es1_data = {
- .gate = &ssi_ssr_gate_fck_3430es1_data,
- .divider = &ssi_ssr_div_fck_3430es1_data,
-};
-
-static struct ti_clk ssi_ssr_fck_3430es1 = {
- .name = "ssi_ssr_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &ssi_ssr_fck_3430es1_data,
-};
-
-static struct ti_clk_fixed_factor ssi_sst_fck_3430es1_data = {
- .parent = "ssi_ssr_fck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk ssi_sst_fck_3430es1 = {
- .name = "ssi_sst_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &ssi_sst_fck_3430es1_data,
-};
-
-static struct ti_clk_fixed omap_32k_fck_data = {
- .frequency = 32768,
-};
-
-static struct ti_clk omap_32k_fck = {
- .name = "omap_32k_fck",
- .type = TI_CLK_FIXED,
- .data = &omap_32k_fck_data,
-};
-
-static struct ti_clk_fixed_factor per_32k_alwon_fck_data = {
- .parent = "omap_32k_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk per_32k_alwon_fck = {
- .name = "per_32k_alwon_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &per_32k_alwon_fck_data,
-};
-
-static struct ti_clk_gate gpio5_dbck_data = {
- .parent = "per_32k_alwon_fck",
- .bit_shift = 16,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk gpio5_dbck = {
- .name = "gpio5_dbck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio5_dbck_data,
-};
-
-static struct ti_clk_gate gpt1_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 0,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt1_ick = {
- .name = "gpt1_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt1_ick_data,
-};
-
-static struct ti_clk_gate mcspi3_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 20,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mcspi3_fck = {
- .name = "mcspi3_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi3_fck_data,
-};
-
-static struct ti_clk_gate gpt2_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 3,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static const char *gpt2_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt2_mux_fck_data = {
- .num_parents = ARRAY_SIZE(gpt2_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt2_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt2_fck_data = {
- .mux = &gpt2_mux_fck_data,
- .gate = &gpt2_gate_fck_data,
-};
-
-static struct ti_clk gpt2_fck = {
- .name = "gpt2_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt2_fck_data,
-};
-
-static struct ti_clk_gate gpt10_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 11,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt10_ick = {
- .name = "gpt10_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt10_ick_data,
-};
-
-static struct ti_clk_gate uart2_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 14,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk uart2_fck = {
- .name = "uart2_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart2_fck_data,
-};
-
-static struct ti_clk_fixed_factor sr_l4_ick_data = {
- .parent = "l4_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk sr_l4_ick = {
- .name = "sr_l4_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &sr_l4_ick_data,
-};
-
-static struct ti_clk_fixed_factor omap_96m_d8_fck_data = {
- .parent = "omap_96m_fck",
- .div = 8,
- .mult = 1,
-};
-
-static struct ti_clk omap_96m_d8_fck = {
- .name = "omap_96m_d8_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_96m_d8_fck_data,
-};
-
-static struct ti_clk_divider dpll4_m5_ck_data = {
- .parent = "dpll4_ck",
- .max_div = 63,
- .reg = 0xf40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll4_m5_ck = {
- .name = "dpll4_m5_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll4_m5_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll4_m5x2_mul_ck_data = {
- .parent = "dpll4_m5_ck",
- .div = 1,
- .mult = 2,
- .flags = CLKF_SET_RATE_PARENT,
-};
-
-static struct ti_clk dpll4_m5x2_mul_ck = {
- .name = "dpll4_m5x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_m5x2_mul_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m5x2_ck_data = {
- .parent = "dpll4_m5x2_mul_ck",
- .bit_shift = 0x1e,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m5x2_ck = {
- .name = "dpll4_m5x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m5x2_ck_data,
-};
-
-static struct ti_clk_gate cam_mclk_data = {
- .parent = "dpll4_m5x2_ck",
- .bit_shift = 0,
- .reg = 0xf00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_RATE_PARENT,
-};
-
-static struct ti_clk cam_mclk = {
- .name = "cam_mclk",
- .type = TI_CLK_GATE,
- .data = &cam_mclk_data,
-};
-
-static struct ti_clk_gate mcbsp3_gate_fck_data = {
- .parent = "mcbsp_clks",
- .bit_shift = 1,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static const char *mcbsp3_mux_fck_parents[] = {
- "per_96m_fck",
- "mcbsp_clks",
-};
-
-static struct ti_clk_mux mcbsp3_mux_fck_data = {
- .num_parents = ARRAY_SIZE(mcbsp3_mux_fck_parents),
- .reg = 0x2d8,
- .module = TI_CLKM_SCRM,
- .parents = mcbsp3_mux_fck_parents,
-};
-
-static struct ti_clk_composite mcbsp3_fck_data = {
- .mux = &mcbsp3_mux_fck_data,
- .gate = &mcbsp3_gate_fck_data,
-};
-
-static struct ti_clk mcbsp3_fck = {
- .name = "mcbsp3_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &mcbsp3_fck_data,
-};
-
-static struct ti_clk_gate csi2_96m_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 1,
- .reg = 0xf00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk csi2_96m_fck = {
- .name = "csi2_96m_fck",
- .clkdm_name = "cam_clkdm",
- .type = TI_CLK_GATE,
- .data = &csi2_96m_fck_data,
-};
-
-static struct ti_clk_gate gpt9_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 10,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static const char *gpt9_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt9_mux_fck_data = {
- .bit_shift = 7,
- .num_parents = ARRAY_SIZE(gpt9_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt9_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt9_fck_data = {
- .mux = &gpt9_mux_fck_data,
- .gate = &gpt9_gate_fck_data,
-};
-
-static struct ti_clk gpt9_fck = {
- .name = "gpt9_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt9_fck_data,
-};
-
-static struct ti_clk_divider dpll3_m3_ck_data = {
- .parent = "dpll3_ck",
- .bit_shift = 16,
- .max_div = 31,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll3_m3_ck = {
- .name = "dpll3_m3_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll3_m3_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll3_m3x2_mul_ck_data = {
- .parent = "dpll3_m3_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll3_m3x2_mul_ck = {
- .name = "dpll3_m3x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll3_m3x2_mul_ck_data,
-};
-
-static struct ti_clk_gate sr2_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 7,
- .reg = 0xc00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk sr2_fck = {
- .name = "sr2_fck",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &sr2_fck_data,
-};
-
-static struct ti_clk_fixed pclk_ck_data = {
- .frequency = 27000000,
-};
-
-static struct ti_clk pclk_ck = {
- .name = "pclk_ck",
- .type = TI_CLK_FIXED,
- .data = &pclk_ck_data,
-};
-
-static struct ti_clk_gate wdt2_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 5,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk wdt2_ick = {
- .name = "wdt2_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &wdt2_ick_data,
-};
-
-static struct ti_clk_fixed_factor core_l3_ick_data = {
- .parent = "l3_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_l3_ick = {
- .name = "core_l3_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_l3_ick_data,
-};
-
-static struct ti_clk_gate mcspi4_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 21,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mcspi4_fck = {
- .name = "mcspi4_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi4_fck_data,
-};
-
-static struct ti_clk_fixed_factor per_48m_fck_data = {
- .parent = "omap_48m_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk per_48m_fck = {
- .name = "per_48m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &per_48m_fck_data,
-};
-
-static struct ti_clk_gate uart4_fck_data = {
- .parent = "per_48m_fck",
- .bit_shift = 18,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk uart4_fck = {
- .name = "uart4_fck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart4_fck_data,
-};
-
-static struct ti_clk_fixed_factor omap_96m_d10_fck_data = {
- .parent = "omap_96m_fck",
- .div = 10,
- .mult = 1,
-};
-
-static struct ti_clk omap_96m_d10_fck = {
- .name = "omap_96m_d10_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_96m_d10_fck_data,
-};
-
-static struct ti_clk_gate usim_gate_fck_data = {
- .parent = "omap_96m_fck",
- .bit_shift = 9,
- .reg = 0xc00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_fixed_factor per_l4_ick_data = {
- .parent = "l4_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk per_l4_ick = {
- .name = "per_l4_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &per_l4_ick_data,
-};
-
-static struct ti_clk_gate gpt5_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 6,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt5_ick = {
- .name = "gpt5_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt5_ick_data,
-};
-
-static struct ti_clk_gate mcspi2_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 19,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcspi2_ick = {
- .name = "mcspi2_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi2_ick_data,
-};
-
-static struct ti_clk_fixed_factor ssi_l4_ick_data = {
- .parent = "l4_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk ssi_l4_ick = {
- .name = "ssi_l4_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &ssi_l4_ick_data,
-};
-
-static struct ti_clk_gate ssi_ick_3430es1_data = {
- .parent = "ssi_l4_ick",
- .bit_shift = 0,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
-};
-
-static struct ti_clk ssi_ick_3430es1 = {
- .name = "ssi_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &ssi_ick_3430es1_data,
-};
-
-static struct ti_clk_gate i2c2_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 16,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk i2c2_fck = {
- .name = "i2c2_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &i2c2_fck_data,
-};
-
-static struct ti_clk_divider dpll1_fck_data = {
- .parent = "core_ck",
- .bit_shift = 19,
- .max_div = 7,
- .reg = 0x940,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll1_fck = {
- .name = "dpll1_fck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll1_fck_data,
-};
-
-static const char *dpll1_ck_parents[] = {
- "sys_ck",
- "dpll1_fck",
-};
-
-static struct ti_clk_dpll dpll1_ck_data = {
- .num_parents = ARRAY_SIZE(dpll1_ck_parents),
- .control_reg = 0x904,
- .idlest_reg = 0x924,
- .mult_div1_reg = 0x940,
- .autoidle_reg = 0x934,
- .module = TI_CLKM_CM,
- .parents = dpll1_ck_parents,
- .freqsel_mask = 0xf0,
- .modes = 0xa0,
- .div1_mask = 0x7f,
- .idlest_mask = 0x1,
- .auto_recal_bit = 0x3,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x7,
- .max_multiplier = 0x7ff,
- .enable_mask = 0x7,
- .mult_mask = 0x7ff00,
- .recal_st_bit = 0x7,
- .autoidle_mask = 0x7,
-};
-
-static struct ti_clk dpll1_ck = {
- .name = "dpll1_ck",
- .clkdm_name = "dpll1_clkdm",
- .type = TI_CLK_DPLL,
- .data = &dpll1_ck_data,
-};
-
-static struct ti_clk_fixed secure_32k_fck_data = {
- .frequency = 32768,
-};
-
-static struct ti_clk secure_32k_fck = {
- .name = "secure_32k_fck",
- .type = TI_CLK_FIXED,
- .data = &secure_32k_fck_data,
-};
-
-static struct ti_clk_gate gpio5_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 16,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio5_ick = {
- .name = "gpio5_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio5_ick_data,
-};
-
-static struct ti_clk_divider dpll4_m4_ck_data = {
- .parent = "dpll4_ck",
- .max_div = 32,
- .reg = 0xe40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll4_m4_ck = {
- .name = "dpll4_m4_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll4_m4_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll4_m4x2_mul_ck_data = {
- .parent = "dpll4_m4_ck",
- .div = 1,
- .mult = 2,
- .flags = CLKF_SET_RATE_PARENT,
-};
-
-static struct ti_clk dpll4_m4x2_mul_ck = {
- .name = "dpll4_m4x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_m4x2_mul_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m4x2_ck_data = {
- .parent = "dpll4_m4x2_mul_ck",
- .bit_shift = 0x1d,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m4x2_ck = {
- .name = "dpll4_m4x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m4x2_ck_data,
-};
-
-static struct ti_clk_gate dss1_alwon_fck_3430es2_data = {
- .parent = "dpll4_m4x2_ck",
- .bit_shift = 0,
- .reg = 0xe00,
- .module = TI_CLKM_CM,
- .flags = CLKF_DSS | CLKF_SET_RATE_PARENT,
-};
-
-static struct ti_clk dss1_alwon_fck_3430es2 = {
- .name = "dss1_alwon_fck",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss1_alwon_fck_3430es2_data,
-};
-
-static struct ti_clk_gate uart3_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 11,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk uart3_ick = {
- .name = "uart3_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart3_ick_data,
-};
-
-static struct ti_clk_divider dpll4_m3_ck_data = {
- .parent = "dpll4_ck",
- .bit_shift = 8,
- .max_div = 32,
- .reg = 0xe40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll4_m3_ck = {
- .name = "dpll4_m3_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll4_m3_ck_data,
-};
-
-static struct ti_clk_gate mcbsp3_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 1,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcbsp3_ick = {
- .name = "mcbsp3_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcbsp3_ick_data,
-};
-
-static struct ti_clk_gate gpio3_dbck_data = {
- .parent = "per_32k_alwon_fck",
- .bit_shift = 14,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk gpio3_dbck = {
- .name = "gpio3_dbck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio3_dbck_data,
-};
-
-static struct ti_clk_gate fac_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 8,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk fac_ick = {
- .name = "fac_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &fac_ick_data,
-};
-
-static struct ti_clk_gate clkout2_src_gate_ck_data = {
- .parent = "core_ck",
- .bit_shift = 7,
- .reg = 0xd70,
- .module = TI_CLKM_CM,
- .flags = CLKF_NO_WAIT,
-};
-
-static struct ti_clk_fixed_factor dpll4_m3x2_mul_ck_data = {
- .parent = "dpll4_m3_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll4_m3x2_mul_ck = {
- .name = "dpll4_m3x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_m3x2_mul_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m3x2_ck_data = {
- .parent = "dpll4_m3x2_mul_ck",
- .bit_shift = 0x1c,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m3x2_ck = {
- .name = "dpll4_m3x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m3x2_ck_data,
-};
-
-static const char *omap_54m_fck_parents[] = {
- "dpll4_m3x2_ck",
- "sys_altclk",
-};
-
-static struct ti_clk_mux omap_54m_fck_data = {
- .bit_shift = 5,
- .num_parents = ARRAY_SIZE(omap_54m_fck_parents),
- .reg = 0xd40,
- .module = TI_CLKM_CM,
- .parents = omap_54m_fck_parents,
-};
-
-static struct ti_clk omap_54m_fck = {
- .name = "omap_54m_fck",
- .type = TI_CLK_MUX,
- .data = &omap_54m_fck_data,
-};
-
-static const char *clkout2_src_mux_ck_parents[] = {
- "core_ck",
- "sys_ck",
- "cm_96m_fck",
- "omap_54m_fck",
-};
-
-static struct ti_clk_mux clkout2_src_mux_ck_data = {
- .num_parents = ARRAY_SIZE(clkout2_src_mux_ck_parents),
- .reg = 0xd70,
- .module = TI_CLKM_CM,
- .parents = clkout2_src_mux_ck_parents,
-};
-
-static struct ti_clk_composite clkout2_src_ck_data = {
- .mux = &clkout2_src_mux_ck_data,
- .gate = &clkout2_src_gate_ck_data,
-};
-
-static struct ti_clk clkout2_src_ck = {
- .name = "clkout2_src_ck",
- .type = TI_CLK_COMPOSITE,
- .data = &clkout2_src_ck_data,
-};
-
-static struct ti_clk_gate i2c1_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 15,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk i2c1_fck = {
- .name = "i2c1_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &i2c1_fck_data,
-};
-
-static struct ti_clk_gate wdt3_fck_data = {
- .parent = "per_32k_alwon_fck",
- .bit_shift = 12,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk wdt3_fck = {
- .name = "wdt3_fck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &wdt3_fck_data,
-};
-
-static struct ti_clk_gate gpt7_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 8,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static const char *gpt7_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt7_mux_fck_data = {
- .bit_shift = 5,
- .num_parents = ARRAY_SIZE(gpt7_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt7_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt7_fck_data = {
- .mux = &gpt7_mux_fck_data,
- .gate = &gpt7_gate_fck_data,
-};
-
-static struct ti_clk gpt7_fck = {
- .name = "gpt7_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt7_fck_data,
-};
-
-static struct ti_clk_gate usb_l4_gate_ick_data = {
- .parent = "l4_ick",
- .bit_shift = 5,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_INTERFACE,
-};
-
-static struct ti_clk_divider usb_l4_div_ick_data = {
- .parent = "l4_ick",
- .bit_shift = 4,
- .max_div = 1,
- .reg = 0xa40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk_composite usb_l4_ick_data = {
- .gate = &usb_l4_gate_ick_data,
- .divider = &usb_l4_div_ick_data,
-};
-
-static struct ti_clk usb_l4_ick = {
- .name = "usb_l4_ick",
- .type = TI_CLK_COMPOSITE,
- .data = &usb_l4_ick_data,
-};
-
-static struct ti_clk_gate uart4_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 18,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk uart4_ick = {
- .name = "uart4_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart4_ick_data,
-};
-
-static struct ti_clk_fixed dummy_ck_data = {
- .frequency = 0,
-};
-
-static struct ti_clk dummy_ck = {
- .name = "dummy_ck",
- .type = TI_CLK_FIXED,
- .data = &dummy_ck_data,
-};
-
-static const char *gpt3_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt3_mux_fck_data = {
- .bit_shift = 1,
- .num_parents = ARRAY_SIZE(gpt3_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt3_mux_fck_parents,
-};
-
-static struct ti_clk_gate gpt9_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 10,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt9_ick = {
- .name = "gpt9_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt9_ick_data,
-};
-
-static struct ti_clk_gate gpt10_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 11,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_gate dss_ick_3430es1_data = {
- .parent = "l4_ick",
- .bit_shift = 0,
- .reg = 0xe10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
-};
-
-static struct ti_clk dss_ick_3430es1 = {
- .name = "dss_ick",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss_ick_3430es1_data,
-};
-
-static struct ti_clk_gate gpt11_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 12,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt11_ick = {
- .name = "gpt11_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt11_ick_data,
-};
-
-static struct ti_clk_divider dpll2_fck_data = {
- .parent = "core_ck",
- .bit_shift = 19,
- .max_div = 7,
- .reg = 0x40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll2_fck = {
- .name = "dpll2_fck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll2_fck_data,
-};
-
-static struct ti_clk_gate uart1_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 13,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk uart1_fck = {
- .name = "uart1_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart1_fck_data,
-};
-
-static struct ti_clk_gate hsotgusb_ick_3430es1_data = {
- .parent = "core_l3_ick",
- .bit_shift = 4,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
-};
-
-static struct ti_clk hsotgusb_ick_3430es1 = {
- .name = "hsotgusb_ick_3430es1",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &hsotgusb_ick_3430es1_data,
-};
-
-static struct ti_clk_gate gpio2_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 13,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio2_ick = {
- .name = "gpio2_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio2_ick_data,
-};
-
-static struct ti_clk_gate mmchs1_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 24,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mmchs1_ick = {
- .name = "mmchs1_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs1_ick_data,
-};
-
-static struct ti_clk_gate modem_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 31,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk modem_fck = {
- .name = "modem_fck",
- .clkdm_name = "d2d_clkdm",
- .type = TI_CLK_GATE,
- .data = &modem_fck_data,
-};
-
-static struct ti_clk_gate mcbsp4_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 2,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcbsp4_ick = {
- .name = "mcbsp4_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcbsp4_ick_data,
-};
-
-static struct ti_clk_gate gpio1_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 3,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio1_ick = {
- .name = "gpio1_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio1_ick_data,
-};
-
-static const char *gpt6_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt6_mux_fck_data = {
- .bit_shift = 4,
- .num_parents = ARRAY_SIZE(gpt6_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt6_mux_fck_parents,
-};
-
-static struct ti_clk_fixed_factor dpll1_x2_ck_data = {
- .parent = "dpll1_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll1_x2_ck = {
- .name = "dpll1_x2_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll1_x2_ck_data,
-};
-
-static struct ti_clk_divider dpll1_x2m2_ck_data = {
- .parent = "dpll1_x2_ck",
- .max_div = 31,
- .reg = 0x944,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll1_x2m2_ck = {
- .name = "dpll1_x2m2_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll1_x2m2_ck_data,
-};
-
-static struct ti_clk_fixed_factor mpu_ck_data = {
- .parent = "dpll1_x2m2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk mpu_ck = {
- .name = "mpu_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &mpu_ck_data,
-};
-
-static struct ti_clk_divider arm_fck_data = {
- .parent = "mpu_ck",
- .max_div = 2,
- .reg = 0x924,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk arm_fck = {
- .name = "arm_fck",
- .type = TI_CLK_DIVIDER,
- .data = &arm_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_d3_ck_data = {
- .parent = "core_ck",
- .div = 3,
- .mult = 1,
-};
-
-static struct ti_clk core_d3_ck = {
- .name = "core_d3_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_d3_ck_data,
-};
-
-static struct ti_clk_gate gpt11_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 12,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
-};
-
-static const char *gpt11_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt11_mux_fck_data = {
- .bit_shift = 7,
- .num_parents = ARRAY_SIZE(gpt11_mux_fck_parents),
- .reg = 0xa40,
- .module = TI_CLKM_CM,
- .parents = gpt11_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt11_fck_data = {
- .mux = &gpt11_mux_fck_data,
- .gate = &gpt11_gate_fck_data,
-};
-
-static struct ti_clk gpt11_fck = {
- .name = "gpt11_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt11_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_d6_ck_data = {
- .parent = "core_ck",
- .div = 6,
- .mult = 1,
-};
-
-static struct ti_clk core_d6_ck = {
- .name = "core_d6_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_d6_ck_data,
-};
-
-static struct ti_clk_gate uart4_fck_am35xx_data = {
- .parent = "core_48m_fck",
- .bit_shift = 23,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk uart4_fck_am35xx = {
- .name = "uart4_fck_am35xx",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart4_fck_am35xx_data,
-};
-
-static struct ti_clk_gate dpll3_m3x2_ck_data = {
- .parent = "dpll3_m3x2_mul_ck",
- .bit_shift = 0xc,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll3_m3x2_ck = {
- .name = "dpll3_m3x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll3_m3x2_ck_data,
-};
-
-static struct ti_clk_fixed_factor emu_core_alwon_ck_data = {
- .parent = "dpll3_m3x2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk emu_core_alwon_ck = {
- .name = "emu_core_alwon_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &emu_core_alwon_ck_data,
-};
-
-static struct ti_clk_divider dpll4_m6_ck_data = {
- .parent = "dpll4_ck",
- .bit_shift = 24,
- .max_div = 63,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll4_m6_ck = {
- .name = "dpll4_m6_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll4_m6_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll4_m6x2_mul_ck_data = {
- .parent = "dpll4_m6_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll4_m6x2_mul_ck = {
- .name = "dpll4_m6x2_mul_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_m6x2_mul_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m6x2_ck_data = {
- .parent = "dpll4_m6x2_mul_ck",
- .bit_shift = 0x1f,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m6x2_ck = {
- .name = "dpll4_m6x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m6x2_ck_data,
-};
-
-static struct ti_clk_fixed_factor emu_per_alwon_ck_data = {
- .parent = "dpll4_m6x2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk emu_per_alwon_ck = {
- .name = "emu_per_alwon_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &emu_per_alwon_ck_data,
-};
-
-static struct ti_clk_fixed_factor emu_mpu_alwon_ck_data = {
- .parent = "mpu_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk emu_mpu_alwon_ck = {
- .name = "emu_mpu_alwon_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &emu_mpu_alwon_ck_data,
-};
-
-static const char *emu_src_mux_ck_parents[] = {
- "sys_ck",
- "emu_core_alwon_ck",
- "emu_per_alwon_ck",
- "emu_mpu_alwon_ck",
-};
-
-static struct ti_clk_mux emu_src_mux_ck_data = {
- .num_parents = ARRAY_SIZE(emu_src_mux_ck_parents),
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .parents = emu_src_mux_ck_parents,
-};
-
-static struct ti_clk emu_src_mux_ck = {
- .name = "emu_src_mux_ck",
- .type = TI_CLK_MUX,
- .data = &emu_src_mux_ck_data,
-};
-
-static struct ti_clk_gate emu_src_ck_data = {
- .parent = "emu_src_mux_ck",
- .flags = CLKF_CLKDM,
-};
-
-static struct ti_clk emu_src_ck = {
- .name = "emu_src_ck",
- .clkdm_name = "emu_clkdm",
- .type = TI_CLK_GATE,
- .data = &emu_src_ck_data,
-};
-
-static struct ti_clk_divider atclk_fck_data = {
- .parent = "emu_src_ck",
- .bit_shift = 4,
- .max_div = 3,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk atclk_fck = {
- .name = "atclk_fck",
- .type = TI_CLK_DIVIDER,
- .data = &atclk_fck_data,
-};
-
-static struct ti_clk_gate ipss_ick_data = {
- .parent = "core_l3_ick",
- .bit_shift = 4,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_AM35XX | CLKF_INTERFACE,
-};
-
-static struct ti_clk ipss_ick = {
- .name = "ipss_ick",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &ipss_ick_data,
-};
-
-static struct ti_clk_gate emac_ick_data = {
- .parent = "ipss_ick",
- .bit_shift = 1,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
- .flags = CLKF_AM35XX,
-};
-
-static struct ti_clk emac_ick = {
- .name = "emac_ick",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &emac_ick_data,
-};
-
-static struct ti_clk_gate vpfe_ick_data = {
- .parent = "ipss_ick",
- .bit_shift = 2,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
- .flags = CLKF_AM35XX,
-};
-
-static struct ti_clk vpfe_ick = {
- .name = "vpfe_ick",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &vpfe_ick_data,
-};
-
-static const char *dpll2_ck_parents[] = {
- "sys_ck",
- "dpll2_fck",
-};
-
-static struct ti_clk_dpll dpll2_ck_data = {
- .num_parents = ARRAY_SIZE(dpll2_ck_parents),
- .control_reg = 0x4,
- .idlest_reg = 0x24,
- .mult_div1_reg = 0x40,
- .autoidle_reg = 0x34,
- .module = TI_CLKM_CM,
- .parents = dpll2_ck_parents,
- .freqsel_mask = 0xf0,
- .modes = 0xa2,
- .div1_mask = 0x7f,
- .idlest_mask = 0x1,
- .auto_recal_bit = 0x3,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x8,
- .max_multiplier = 0x7ff,
- .enable_mask = 0x7,
- .mult_mask = 0x7ff00,
- .recal_st_bit = 0x8,
- .autoidle_mask = 0x7,
-};
-
-static struct ti_clk dpll2_ck = {
- .name = "dpll2_ck",
- .clkdm_name = "dpll2_clkdm",
- .type = TI_CLK_DPLL,
- .data = &dpll2_ck_data,
-};
-
-static struct ti_clk_divider dpll2_m2_ck_data = {
- .parent = "dpll2_ck",
- .max_div = 31,
- .reg = 0x44,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk dpll2_m2_ck = {
- .name = "dpll2_m2_ck",
- .type = TI_CLK_DIVIDER,
- .data = &dpll2_m2_ck_data,
-};
-
-static const char *mcbsp4_mux_fck_parents[] = {
- "per_96m_fck",
- "mcbsp_clks",
-};
-
-static struct ti_clk_mux mcbsp4_mux_fck_data = {
- .bit_shift = 2,
- .num_parents = ARRAY_SIZE(mcbsp4_mux_fck_parents),
- .reg = 0x2d8,
- .module = TI_CLKM_SCRM,
- .parents = mcbsp4_mux_fck_parents,
-};
-
-static const char *mcbsp1_mux_fck_parents[] = {
- "core_96m_fck",
- "mcbsp_clks",
-};
-
-static struct ti_clk_mux mcbsp1_mux_fck_data = {
- .bit_shift = 2,
- .num_parents = ARRAY_SIZE(mcbsp1_mux_fck_parents),
- .reg = 0x274,
- .module = TI_CLKM_SCRM,
- .parents = mcbsp1_mux_fck_parents,
-};
-
-static struct ti_clk_gate gpt8_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 9,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_gate gpt8_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 9,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt8_ick = {
- .name = "gpt8_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt8_ick_data,
-};
-
-static const char *gpt10_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt10_mux_fck_data = {
- .bit_shift = 6,
- .num_parents = ARRAY_SIZE(gpt10_mux_fck_parents),
- .reg = 0xa40,
- .module = TI_CLKM_CM,
- .parents = gpt10_mux_fck_parents,
-};
-
-static struct ti_clk_gate mmchs3_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 30,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mmchs3_ick = {
- .name = "mmchs3_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs3_ick_data,
-};
-
-static struct ti_clk_gate gpio3_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 14,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio3_ick = {
- .name = "gpio3_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio3_ick_data,
-};
-
-static const char *traceclk_src_fck_parents[] = {
- "sys_ck",
- "emu_core_alwon_ck",
- "emu_per_alwon_ck",
- "emu_mpu_alwon_ck",
-};
-
-static struct ti_clk_mux traceclk_src_fck_data = {
- .bit_shift = 2,
- .num_parents = ARRAY_SIZE(traceclk_src_fck_parents),
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .parents = traceclk_src_fck_parents,
-};
-
-static struct ti_clk traceclk_src_fck = {
- .name = "traceclk_src_fck",
- .type = TI_CLK_MUX,
- .data = &traceclk_src_fck_data,
-};
-
-static struct ti_clk_divider traceclk_fck_data = {
- .parent = "traceclk_src_fck",
- .bit_shift = 11,
- .max_div = 7,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk traceclk_fck = {
- .name = "traceclk_fck",
- .type = TI_CLK_DIVIDER,
- .data = &traceclk_fck_data,
-};
-
-static struct ti_clk_gate mcbsp5_gate_fck_data = {
- .parent = "mcbsp_clks",
- .bit_shift = 10,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_gate sad2d_ick_data = {
- .parent = "l3_ick",
- .bit_shift = 3,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk sad2d_ick = {
- .name = "sad2d_ick",
- .clkdm_name = "d2d_clkdm",
- .type = TI_CLK_GATE,
- .data = &sad2d_ick_data,
-};
-
-static const char *gpt1_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt1_mux_fck_data = {
- .num_parents = ARRAY_SIZE(gpt1_mux_fck_parents),
- .reg = 0xc40,
- .module = TI_CLKM_CM,
- .parents = gpt1_mux_fck_parents,
-};
-
-static struct ti_clk_gate hecc_ck_data = {
- .parent = "sys_ck",
- .bit_shift = 3,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
- .flags = CLKF_AM35XX,
-};
-
-static struct ti_clk hecc_ck = {
- .name = "hecc_ck",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &hecc_ck_data,
-};
-
-static struct ti_clk_gate gpt1_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 0,
- .reg = 0xc00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_composite gpt1_fck_data = {
- .mux = &gpt1_mux_fck_data,
- .gate = &gpt1_gate_fck_data,
-};
-
-static struct ti_clk gpt1_fck = {
- .name = "gpt1_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt1_fck_data,
-};
-
-static struct ti_clk_gate dpll4_m2x2_ck_omap36xx_data = {
- .parent = "dpll4_m2x2_mul_ck",
- .bit_shift = 0x1b,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m2x2_ck_omap36xx = {
- .name = "dpll4_m2x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m2x2_ck_omap36xx_data,
- .patch = &dpll4_m2x2_ck,
-};
-
-static struct ti_clk_divider gfx_l3_fck_data = {
- .parent = "l3_ick",
- .max_div = 7,
- .reg = 0xb40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk gfx_l3_fck = {
- .name = "gfx_l3_fck",
- .type = TI_CLK_DIVIDER,
- .data = &gfx_l3_fck_data,
-};
-
-static struct ti_clk_gate gfx_cg1_ck_data = {
- .parent = "gfx_l3_fck",
- .bit_shift = 1,
- .reg = 0xb00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk gfx_cg1_ck = {
- .name = "gfx_cg1_ck",
- .clkdm_name = "gfx_3430es1_clkdm",
- .type = TI_CLK_GATE,
- .data = &gfx_cg1_ck_data,
-};
-
-static struct ti_clk_gate mailboxes_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 7,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mailboxes_ick = {
- .name = "mailboxes_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mailboxes_ick_data,
-};
-
-static struct ti_clk_gate sha11_ick_data = {
- .parent = "security_l4_ick2",
- .bit_shift = 1,
- .reg = 0xa14,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk sha11_ick = {
- .name = "sha11_ick",
- .type = TI_CLK_GATE,
- .data = &sha11_ick_data,
-};
-
-static struct ti_clk_gate hsotgusb_ick_am35xx_data = {
- .parent = "ipss_ick",
- .bit_shift = 0,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
- .flags = CLKF_AM35XX,
-};
-
-static struct ti_clk hsotgusb_ick_am35xx = {
- .name = "hsotgusb_ick_am35xx",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &hsotgusb_ick_am35xx_data,
-};
-
-static struct ti_clk_gate mmchs3_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 30,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mmchs3_fck = {
- .name = "mmchs3_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs3_fck_data,
-};
-
-static struct ti_clk_divider pclk_fck_data = {
- .parent = "emu_src_ck",
- .bit_shift = 8,
- .max_div = 7,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk pclk_fck = {
- .name = "pclk_fck",
- .type = TI_CLK_DIVIDER,
- .data = &pclk_fck_data,
-};
-
-static const char *dpll4_ck_omap36xx_parents[] = {
- "sys_ck",
- "sys_ck",
-};
-
-static struct ti_clk_dpll dpll4_ck_omap36xx_data = {
- .num_parents = ARRAY_SIZE(dpll4_ck_omap36xx_parents),
- .control_reg = 0xd00,
- .idlest_reg = 0xd20,
- .mult_div1_reg = 0xd44,
- .autoidle_reg = 0xd30,
- .module = TI_CLKM_CM,
- .parents = dpll4_ck_omap36xx_parents,
- .modes = 0x82,
- .div1_mask = 0x7f,
- .idlest_mask = 0x2,
- .auto_recal_bit = 0x13,
- .max_divider = 0x80,
- .min_divider = 0x1,
- .recal_en_bit = 0x6,
- .max_multiplier = 0xfff,
- .enable_mask = 0x70000,
- .mult_mask = 0xfff00,
- .recal_st_bit = 0x6,
- .autoidle_mask = 0x38,
- .sddiv_mask = 0xff000000,
- .dco_mask = 0xe00000,
- .flags = CLKF_PER | CLKF_J_TYPE,
-};
-
-static struct ti_clk dpll4_ck_omap36xx = {
- .name = "dpll4_ck",
- .type = TI_CLK_DPLL,
- .data = &dpll4_ck_omap36xx_data,
- .patch = &dpll4_ck,
-};
-
-static struct ti_clk_gate uart3_fck_data = {
- .parent = "per_48m_fck",
- .bit_shift = 11,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk uart3_fck = {
- .name = "uart3_fck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart3_fck_data,
-};
-
-static struct ti_clk_fixed_factor wkup_32k_fck_data = {
- .parent = "omap_32k_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk wkup_32k_fck = {
- .name = "wkup_32k_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &wkup_32k_fck_data,
-};
-
-static struct ti_clk_gate sys_clkout1_data = {
- .parent = "osc_sys_ck",
- .bit_shift = 7,
- .reg = 0xd70,
- .module = TI_CLKM_PRM,
-};
-
-static struct ti_clk sys_clkout1 = {
- .name = "sys_clkout1",
- .type = TI_CLK_GATE,
- .data = &sys_clkout1_data,
-};
-
-static struct ti_clk_fixed_factor gpmc_fck_data = {
- .parent = "core_l3_ick",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk gpmc_fck = {
- .name = "gpmc_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &gpmc_fck_data,
-};
-
-static struct ti_clk_fixed_factor dpll5_m2_d20_ck_data = {
- .parent = "dpll5_m2_ck",
- .div = 20,
- .mult = 1,
-};
-
-static struct ti_clk dpll5_m2_d20_ck = {
- .name = "dpll5_m2_d20_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll5_m2_d20_ck_data,
-};
-
-static struct ti_clk_gate dpll4_m5x2_ck_omap36xx_data = {
- .parent = "dpll4_m5x2_mul_ck",
- .bit_shift = 0x1e,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_HSDIV | CLKF_SET_RATE_PARENT | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m5x2_ck_omap36xx = {
- .name = "dpll4_m5x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m5x2_ck_omap36xx_data,
- .patch = &dpll4_m5x2_ck,
-};
-
-static struct ti_clk_gate ssi_ssr_gate_fck_3430es2_data = {
- .parent = "corex2_fck",
- .bit_shift = 0,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_NO_WAIT,
-};
-
-static struct ti_clk_gate uart1_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 13,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk uart1_ick = {
- .name = "uart1_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart1_ick_data,
-};
-
-static struct ti_clk_gate iva2_ck_data = {
- .parent = "dpll2_m2_ck",
- .bit_shift = 0,
- .reg = 0x0,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk iva2_ck = {
- .name = "iva2_ck",
- .clkdm_name = "iva2_clkdm",
- .type = TI_CLK_GATE,
- .data = &iva2_ck_data,
-};
-
-static struct ti_clk_gate pka_ick_data = {
- .parent = "security_l3_ick",
- .bit_shift = 4,
- .reg = 0xa14,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk pka_ick = {
- .name = "pka_ick",
- .type = TI_CLK_GATE,
- .data = &pka_ick_data,
-};
-
-static struct ti_clk_gate gpt12_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 1,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt12_ick = {
- .name = "gpt12_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt12_ick_data,
-};
-
-static const char *mcbsp5_mux_fck_parents[] = {
- "core_96m_fck",
- "mcbsp_clks",
-};
-
-static struct ti_clk_mux mcbsp5_mux_fck_data = {
- .bit_shift = 4,
- .num_parents = ARRAY_SIZE(mcbsp5_mux_fck_parents),
- .reg = 0x2d8,
- .module = TI_CLKM_SCRM,
- .parents = mcbsp5_mux_fck_parents,
-};
-
-static struct ti_clk_composite mcbsp5_fck_data = {
- .mux = &mcbsp5_mux_fck_data,
- .gate = &mcbsp5_gate_fck_data,
-};
-
-static struct ti_clk mcbsp5_fck = {
- .name = "mcbsp5_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &mcbsp5_fck_data,
-};
-
-static struct ti_clk_gate usbhost_48m_fck_data = {
- .parent = "omap_48m_fck",
- .bit_shift = 0,
- .reg = 0x1400,
- .module = TI_CLKM_CM,
- .flags = CLKF_DSS,
-};
-
-static struct ti_clk usbhost_48m_fck = {
- .name = "usbhost_48m_fck",
- .clkdm_name = "usbhost_clkdm",
- .type = TI_CLK_GATE,
- .data = &usbhost_48m_fck_data,
-};
-
-static struct ti_clk_gate des1_ick_data = {
- .parent = "security_l4_ick2",
- .bit_shift = 0,
- .reg = 0xa14,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk des1_ick = {
- .name = "des1_ick",
- .type = TI_CLK_GATE,
- .data = &des1_ick_data,
-};
-
-static struct ti_clk_gate sgx_gate_fck_data = {
- .parent = "core_ck",
- .bit_shift = 1,
- .reg = 0xb00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_fixed_factor core_d4_ck_data = {
- .parent = "core_ck",
- .div = 4,
- .mult = 1,
-};
-
-static struct ti_clk core_d4_ck = {
- .name = "core_d4_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_d4_ck_data,
-};
-
-static struct ti_clk_fixed_factor omap_192m_alwon_fck_data = {
- .parent = "dpll4_m2x2_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk omap_192m_alwon_fck = {
- .name = "omap_192m_alwon_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_192m_alwon_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_d2_ck_data = {
- .parent = "core_ck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk core_d2_ck = {
- .name = "core_d2_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_d2_ck_data,
-};
-
-static struct ti_clk_fixed_factor corex2_d3_fck_data = {
- .parent = "corex2_fck",
- .div = 3,
- .mult = 1,
-};
-
-static struct ti_clk corex2_d3_fck = {
- .name = "corex2_d3_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &corex2_d3_fck_data,
-};
-
-static struct ti_clk_fixed_factor corex2_d5_fck_data = {
- .parent = "corex2_fck",
- .div = 5,
- .mult = 1,
-};
-
-static struct ti_clk corex2_d5_fck = {
- .name = "corex2_d5_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &corex2_d5_fck_data,
-};
-
-static const char *sgx_mux_fck_parents[] = {
- "core_d3_ck",
- "core_d4_ck",
- "core_d6_ck",
- "cm_96m_fck",
- "omap_192m_alwon_fck",
- "core_d2_ck",
- "corex2_d3_fck",
- "corex2_d5_fck",
-};
-
-static struct ti_clk_mux sgx_mux_fck_data = {
- .num_parents = ARRAY_SIZE(sgx_mux_fck_parents),
- .reg = 0xb40,
- .module = TI_CLKM_CM,
- .parents = sgx_mux_fck_parents,
-};
-
-static struct ti_clk_composite sgx_fck_data = {
- .mux = &sgx_mux_fck_data,
- .gate = &sgx_gate_fck_data,
-};
-
-static struct ti_clk sgx_fck = {
- .name = "sgx_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &sgx_fck_data,
-};
-
-static struct ti_clk_gate mcspi1_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 18,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mcspi1_fck = {
- .name = "mcspi1_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi1_fck_data,
-};
-
-static struct ti_clk_gate mmchs2_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 25,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mmchs2_fck = {
- .name = "mmchs2_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs2_fck_data,
-};
-
-static struct ti_clk_gate mcspi2_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 19,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mcspi2_fck = {
- .name = "mcspi2_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi2_fck_data,
-};
-
-static struct ti_clk_gate vpfe_fck_data = {
- .parent = "pclk_ck",
- .bit_shift = 10,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
-};
-
-static struct ti_clk vpfe_fck = {
- .name = "vpfe_fck",
- .type = TI_CLK_GATE,
- .data = &vpfe_fck_data,
-};
-
-static struct ti_clk_gate gpt4_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 5,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_gate mcbsp1_gate_fck_data = {
- .parent = "mcbsp_clks",
- .bit_shift = 9,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_gate gpt5_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 6,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static const char *gpt5_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt5_mux_fck_data = {
- .bit_shift = 3,
- .num_parents = ARRAY_SIZE(gpt5_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt5_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt5_fck_data = {
- .mux = &gpt5_mux_fck_data,
- .gate = &gpt5_gate_fck_data,
-};
-
-static struct ti_clk gpt5_fck = {
- .name = "gpt5_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt5_fck_data,
-};
-
-static struct ti_clk_gate ts_fck_data = {
- .parent = "omap_32k_fck",
- .bit_shift = 1,
- .reg = 0xa08,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk ts_fck = {
- .name = "ts_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &ts_fck_data,
-};
-
-static struct ti_clk_fixed_factor wdt1_fck_data = {
- .parent = "secure_32k_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk wdt1_fck = {
- .name = "wdt1_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &wdt1_fck_data,
-};
-
-static struct ti_clk_gate dpll4_m6x2_ck_omap36xx_data = {
- .parent = "dpll4_m6x2_mul_ck",
- .bit_shift = 0x1f,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m6x2_ck_omap36xx = {
- .name = "dpll4_m6x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m6x2_ck_omap36xx_data,
- .patch = &dpll4_m6x2_ck,
-};
-
-static const char *gpt4_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt4_mux_fck_data = {
- .bit_shift = 2,
- .num_parents = ARRAY_SIZE(gpt4_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt4_mux_fck_parents,
-};
-
-static struct ti_clk_gate usbhost_ick_data = {
- .parent = "l4_ick",
- .bit_shift = 0,
- .reg = 0x1410,
- .module = TI_CLKM_CM,
- .flags = CLKF_DSS | CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk usbhost_ick = {
- .name = "usbhost_ick",
- .clkdm_name = "usbhost_clkdm",
- .type = TI_CLK_GATE,
- .data = &usbhost_ick_data,
-};
-
-static struct ti_clk_gate mcbsp2_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 0,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcbsp2_ick = {
- .name = "mcbsp2_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcbsp2_ick_data,
-};
-
-static struct ti_clk_gate omapctrl_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 6,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk omapctrl_ick = {
- .name = "omapctrl_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &omapctrl_ick_data,
-};
-
-static struct ti_clk_fixed_factor omap_96m_d4_fck_data = {
- .parent = "omap_96m_fck",
- .div = 4,
- .mult = 1,
-};
-
-static struct ti_clk omap_96m_d4_fck = {
- .name = "omap_96m_d4_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_96m_d4_fck_data,
-};
-
-static struct ti_clk_gate gpt6_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 7,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt6_ick = {
- .name = "gpt6_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt6_ick_data,
-};
-
-static struct ti_clk_gate dpll3_m3x2_ck_omap36xx_data = {
- .parent = "dpll3_m3x2_mul_ck",
- .bit_shift = 0xc,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll3_m3x2_ck_omap36xx = {
- .name = "dpll3_m3x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll3_m3x2_ck_omap36xx_data,
- .patch = &dpll3_m3x2_ck,
-};
-
-static struct ti_clk_gate i2c3_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 17,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk i2c3_ick = {
- .name = "i2c3_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &i2c3_ick_data,
-};
-
-static struct ti_clk_gate gpio6_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 17,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio6_ick = {
- .name = "gpio6_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio6_ick_data,
-};
-
-static struct ti_clk_gate mspro_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 23,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mspro_ick = {
- .name = "mspro_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mspro_ick_data,
-};
-
-static struct ti_clk_composite mcbsp1_fck_data = {
- .mux = &mcbsp1_mux_fck_data,
- .gate = &mcbsp1_gate_fck_data,
-};
-
-static struct ti_clk mcbsp1_fck = {
- .name = "mcbsp1_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &mcbsp1_fck_data,
-};
-
-static struct ti_clk_gate gpt3_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 4,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_fixed rmii_ck_data = {
- .frequency = 50000000,
-};
-
-static struct ti_clk rmii_ck = {
- .name = "rmii_ck",
- .type = TI_CLK_FIXED,
- .data = &rmii_ck_data,
-};
-
-static struct ti_clk_gate gpt6_gate_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 7,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_composite gpt6_fck_data = {
- .mux = &gpt6_mux_fck_data,
- .gate = &gpt6_gate_fck_data,
-};
-
-static struct ti_clk gpt6_fck = {
- .name = "gpt6_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt6_fck_data,
-};
-
-static struct ti_clk_fixed_factor dpll5_m2_d4_ck_data = {
- .parent = "dpll5_m2_ck",
- .div = 4,
- .mult = 1,
-};
-
-static struct ti_clk dpll5_m2_d4_ck = {
- .name = "dpll5_m2_d4_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll5_m2_d4_ck_data,
-};
-
-static struct ti_clk_fixed_factor sys_d2_ck_data = {
- .parent = "sys_ck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk sys_d2_ck = {
- .name = "sys_d2_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &sys_d2_ck_data,
-};
-
-static struct ti_clk_fixed_factor omap_96m_d2_fck_data = {
- .parent = "omap_96m_fck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk omap_96m_d2_fck = {
- .name = "omap_96m_d2_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_96m_d2_fck_data,
-};
-
-static struct ti_clk_fixed_factor dpll5_m2_d8_ck_data = {
- .parent = "dpll5_m2_ck",
- .div = 8,
- .mult = 1,
-};
-
-static struct ti_clk dpll5_m2_d8_ck = {
- .name = "dpll5_m2_d8_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll5_m2_d8_ck_data,
-};
-
-static struct ti_clk_fixed_factor dpll5_m2_d16_ck_data = {
- .parent = "dpll5_m2_ck",
- .div = 16,
- .mult = 1,
-};
-
-static struct ti_clk dpll5_m2_d16_ck = {
- .name = "dpll5_m2_d16_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll5_m2_d16_ck_data,
-};
-
-static const char *usim_mux_fck_parents[] = {
- "sys_ck",
- "sys_d2_ck",
- "omap_96m_d2_fck",
- "omap_96m_d4_fck",
- "omap_96m_d8_fck",
- "omap_96m_d10_fck",
- "dpll5_m2_d4_ck",
- "dpll5_m2_d8_ck",
- "dpll5_m2_d16_ck",
- "dpll5_m2_d20_ck",
-};
-
-static struct ti_clk_mux usim_mux_fck_data = {
- .bit_shift = 3,
- .num_parents = ARRAY_SIZE(usim_mux_fck_parents),
- .reg = 0xc40,
- .module = TI_CLKM_CM,
- .parents = usim_mux_fck_parents,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk_composite usim_fck_data = {
- .mux = &usim_mux_fck_data,
- .gate = &usim_gate_fck_data,
-};
-
-static struct ti_clk usim_fck = {
- .name = "usim_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &usim_fck_data,
-};
-
-static int ssi_ssr_div_fck_3430es2_divs[] = {
- 0,
- 1,
- 2,
- 3,
- 4,
- 0,
- 6,
- 0,
- 8,
-};
-
-static struct ti_clk_divider ssi_ssr_div_fck_3430es2_data = {
- .num_dividers = ARRAY_SIZE(ssi_ssr_div_fck_3430es2_divs),
- .parent = "corex2_fck",
- .bit_shift = 8,
- .dividers = ssi_ssr_div_fck_3430es2_divs,
- .reg = 0xa40,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_composite ssi_ssr_fck_3430es2_data = {
- .gate = &ssi_ssr_gate_fck_3430es2_data,
- .divider = &ssi_ssr_div_fck_3430es2_data,
-};
-
-static struct ti_clk ssi_ssr_fck_3430es2 = {
- .name = "ssi_ssr_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &ssi_ssr_fck_3430es2_data,
-};
-
-static struct ti_clk_gate dss1_alwon_fck_3430es1_data = {
- .parent = "dpll4_m4x2_ck",
- .bit_shift = 0,
- .reg = 0xe00,
- .module = TI_CLKM_CM,
- .flags = CLKF_SET_RATE_PARENT,
-};
-
-static struct ti_clk dss1_alwon_fck_3430es1 = {
- .name = "dss1_alwon_fck",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss1_alwon_fck_3430es1_data,
-};
-
-static struct ti_clk_gate gpt3_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 4,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt3_ick = {
- .name = "gpt3_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt3_ick_data,
-};
-
-static struct ti_clk_fixed_factor omap_12m_fck_data = {
- .parent = "omap_48m_fck",
- .div = 4,
- .mult = 1,
-};
-
-static struct ti_clk omap_12m_fck = {
- .name = "omap_12m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &omap_12m_fck_data,
-};
-
-static struct ti_clk_fixed_factor core_12m_fck_data = {
- .parent = "omap_12m_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk core_12m_fck = {
- .name = "core_12m_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &core_12m_fck_data,
-};
-
-static struct ti_clk_gate hdq_fck_data = {
- .parent = "core_12m_fck",
- .bit_shift = 22,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk hdq_fck = {
- .name = "hdq_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &hdq_fck_data,
-};
-
-static struct ti_clk_gate usbtll_fck_data = {
- .parent = "dpll5_m2_ck",
- .bit_shift = 2,
- .reg = 0xa08,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk usbtll_fck = {
- .name = "usbtll_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &usbtll_fck_data,
-};
-
-static struct ti_clk_gate hsotgusb_fck_am35xx_data = {
- .parent = "sys_ck",
- .bit_shift = 8,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
-};
-
-static struct ti_clk hsotgusb_fck_am35xx = {
- .name = "hsotgusb_fck_am35xx",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &hsotgusb_fck_am35xx_data,
-};
-
-static struct ti_clk_gate hsotgusb_ick_3430es2_data = {
- .parent = "core_l3_ick",
- .bit_shift = 4,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_HSOTGUSB | CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk hsotgusb_ick_3430es2 = {
- .name = "hsotgusb_ick_3430es2",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &hsotgusb_ick_3430es2_data,
-};
-
-static struct ti_clk_gate gfx_l3_ck_data = {
- .parent = "l3_ick",
- .bit_shift = 0,
- .reg = 0xb10,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk gfx_l3_ck = {
- .name = "gfx_l3_ck",
- .clkdm_name = "gfx_3430es1_clkdm",
- .type = TI_CLK_GATE,
- .data = &gfx_l3_ck_data,
-};
-
-static struct ti_clk_fixed_factor gfx_l3_ick_data = {
- .parent = "gfx_l3_ck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk gfx_l3_ick = {
- .name = "gfx_l3_ick",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &gfx_l3_ick_data,
-};
-
-static struct ti_clk_gate mcbsp1_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 9,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcbsp1_ick = {
- .name = "mcbsp1_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcbsp1_ick_data,
-};
-
-static struct ti_clk_fixed_factor gpt12_fck_data = {
- .parent = "secure_32k_fck",
- .div = 1,
- .mult = 1,
-};
-
-static struct ti_clk gpt12_fck = {
- .name = "gpt12_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &gpt12_fck_data,
-};
-
-static struct ti_clk_gate gfx_cg2_ck_data = {
- .parent = "gfx_l3_fck",
- .bit_shift = 2,
- .reg = 0xb00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk gfx_cg2_ck = {
- .name = "gfx_cg2_ck",
- .clkdm_name = "gfx_3430es1_clkdm",
- .type = TI_CLK_GATE,
- .data = &gfx_cg2_ck_data,
-};
-
-static struct ti_clk_gate i2c2_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 16,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk i2c2_ick = {
- .name = "i2c2_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &i2c2_ick_data,
-};
-
-static struct ti_clk_gate gpio4_dbck_data = {
- .parent = "per_32k_alwon_fck",
- .bit_shift = 15,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk gpio4_dbck = {
- .name = "gpio4_dbck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio4_dbck_data,
-};
-
-static struct ti_clk_gate i2c3_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 17,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk i2c3_fck = {
- .name = "i2c3_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &i2c3_fck_data,
-};
-
-static struct ti_clk_composite gpt3_fck_data = {
- .mux = &gpt3_mux_fck_data,
- .gate = &gpt3_gate_fck_data,
-};
-
-static struct ti_clk gpt3_fck = {
- .name = "gpt3_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt3_fck_data,
-};
-
-static struct ti_clk_gate i2c1_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 15,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk i2c1_ick = {
- .name = "i2c1_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &i2c1_ick_data,
-};
-
-static struct ti_clk_gate omap_32ksync_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 2,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk omap_32ksync_ick = {
- .name = "omap_32ksync_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &omap_32ksync_ick_data,
-};
-
-static struct ti_clk_gate aes2_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 28,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk aes2_ick = {
- .name = "aes2_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &aes2_ick_data,
-};
-
-static const char *gpt8_mux_fck_parents[] = {
- "omap_32k_fck",
- "sys_ck",
-};
-
-static struct ti_clk_mux gpt8_mux_fck_data = {
- .bit_shift = 6,
- .num_parents = ARRAY_SIZE(gpt8_mux_fck_parents),
- .reg = 0x1040,
- .module = TI_CLKM_CM,
- .parents = gpt8_mux_fck_parents,
-};
-
-static struct ti_clk_composite gpt8_fck_data = {
- .mux = &gpt8_mux_fck_data,
- .gate = &gpt8_gate_fck_data,
-};
-
-static struct ti_clk gpt8_fck = {
- .name = "gpt8_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt8_fck_data,
-};
-
-static struct ti_clk_gate mcbsp4_gate_fck_data = {
- .parent = "mcbsp_clks",
- .bit_shift = 2,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk_composite mcbsp4_fck_data = {
- .mux = &mcbsp4_mux_fck_data,
- .gate = &mcbsp4_gate_fck_data,
-};
-
-static struct ti_clk mcbsp4_fck = {
- .name = "mcbsp4_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &mcbsp4_fck_data,
-};
-
-static struct ti_clk_gate gpio2_dbck_data = {
- .parent = "per_32k_alwon_fck",
- .bit_shift = 13,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk gpio2_dbck = {
- .name = "gpio2_dbck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio2_dbck_data,
-};
-
-static struct ti_clk_gate usbtll_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 2,
- .reg = 0xa18,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk usbtll_ick = {
- .name = "usbtll_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &usbtll_ick_data,
-};
-
-static struct ti_clk_gate mcspi4_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 21,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcspi4_ick = {
- .name = "mcspi4_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi4_ick_data,
-};
-
-static struct ti_clk_gate dss_96m_fck_data = {
- .parent = "omap_96m_fck",
- .bit_shift = 2,
- .reg = 0xe00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk dss_96m_fck = {
- .name = "dss_96m_fck",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss_96m_fck_data,
-};
-
-static struct ti_clk_divider rm_ick_data = {
- .parent = "l4_ick",
- .bit_shift = 1,
- .max_div = 3,
- .reg = 0xc40,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk rm_ick = {
- .name = "rm_ick",
- .type = TI_CLK_DIVIDER,
- .data = &rm_ick_data,
-};
-
-static struct ti_clk_gate hdq_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 22,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk hdq_ick = {
- .name = "hdq_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &hdq_ick_data,
-};
-
-static struct ti_clk_fixed_factor dpll3_x2_ck_data = {
- .parent = "dpll3_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll3_x2_ck = {
- .name = "dpll3_x2_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll3_x2_ck_data,
-};
-
-static struct ti_clk_gate mad2d_ick_data = {
- .parent = "l3_ick",
- .bit_shift = 3,
- .reg = 0xa18,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mad2d_ick = {
- .name = "mad2d_ick",
- .clkdm_name = "d2d_clkdm",
- .type = TI_CLK_GATE,
- .data = &mad2d_ick_data,
-};
-
-static struct ti_clk_gate fshostusb_fck_data = {
- .parent = "core_48m_fck",
- .bit_shift = 5,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk fshostusb_fck = {
- .name = "fshostusb_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &fshostusb_fck_data,
-};
-
-static struct ti_clk_gate sr1_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 6,
- .reg = 0xc00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk sr1_fck = {
- .name = "sr1_fck",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &sr1_fck_data,
-};
-
-static struct ti_clk_gate des2_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 26,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk des2_ick = {
- .name = "des2_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &des2_ick_data,
-};
-
-static struct ti_clk_gate sdrc_ick_data = {
- .parent = "core_l3_ick",
- .bit_shift = 1,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk sdrc_ick = {
- .name = "sdrc_ick",
- .clkdm_name = "core_l3_clkdm",
- .type = TI_CLK_GATE,
- .data = &sdrc_ick_data,
-};
-
-static struct ti_clk_composite gpt4_fck_data = {
- .mux = &gpt4_mux_fck_data,
- .gate = &gpt4_gate_fck_data,
-};
-
-static struct ti_clk gpt4_fck = {
- .name = "gpt4_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt4_fck_data,
-};
-
-static struct ti_clk_gate dpll4_m3x2_ck_omap36xx_data = {
- .parent = "dpll4_m3x2_mul_ck",
- .bit_shift = 0x1c,
- .reg = 0xd00,
- .module = TI_CLKM_CM,
- .flags = CLKF_HSDIV | CLKF_SET_BIT_TO_DISABLE,
-};
-
-static struct ti_clk dpll4_m3x2_ck_omap36xx = {
- .name = "dpll4_m3x2_ck",
- .type = TI_CLK_GATE,
- .data = &dpll4_m3x2_ck_omap36xx_data,
- .patch = &dpll4_m3x2_ck,
-};
-
-static struct ti_clk_gate cpefuse_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 0,
- .reg = 0xa08,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk cpefuse_fck = {
- .name = "cpefuse_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &cpefuse_fck_data,
-};
-
-static struct ti_clk_gate mcspi3_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 20,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcspi3_ick = {
- .name = "mcspi3_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi3_ick_data,
-};
-
-static struct ti_clk_fixed_factor ssi_sst_fck_3430es2_data = {
- .parent = "ssi_ssr_fck",
- .div = 2,
- .mult = 1,
-};
-
-static struct ti_clk ssi_sst_fck_3430es2 = {
- .name = "ssi_sst_fck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &ssi_sst_fck_3430es2_data,
-};
-
-static struct ti_clk_gate gpio1_dbck_data = {
- .parent = "wkup_32k_fck",
- .bit_shift = 3,
- .reg = 0xc00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk gpio1_dbck = {
- .name = "gpio1_dbck",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio1_dbck_data,
-};
-
-static struct ti_clk_gate gpt4_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 5,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt4_ick = {
- .name = "gpt4_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt4_ick_data,
-};
-
-static struct ti_clk_gate gpt2_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 3,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt2_ick = {
- .name = "gpt2_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt2_ick_data,
-};
-
-static struct ti_clk_gate mmchs1_fck_data = {
- .parent = "core_96m_fck",
- .bit_shift = 24,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk mmchs1_fck = {
- .name = "mmchs1_fck",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mmchs1_fck_data,
-};
-
-static struct ti_clk_fixed dummy_apb_pclk_data = {
- .frequency = 0x0,
-};
-
-static struct ti_clk dummy_apb_pclk = {
- .name = "dummy_apb_pclk",
- .type = TI_CLK_FIXED,
- .data = &dummy_apb_pclk_data,
-};
-
-static struct ti_clk_gate gpio6_dbck_data = {
- .parent = "per_32k_alwon_fck",
- .bit_shift = 17,
- .reg = 0x1000,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk gpio6_dbck = {
- .name = "gpio6_dbck",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio6_dbck_data,
-};
-
-static struct ti_clk_gate uart2_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 14,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk uart2_ick = {
- .name = "uart2_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &uart2_ick_data,
-};
-
-static struct ti_clk_fixed_factor dpll4_x2_ck_data = {
- .parent = "dpll4_ck",
- .div = 1,
- .mult = 2,
-};
-
-static struct ti_clk dpll4_x2_ck = {
- .name = "dpll4_x2_ck",
- .type = TI_CLK_FIXED_FACTOR,
- .data = &dpll4_x2_ck_data,
-};
-
-static struct ti_clk_gate gpt7_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 8,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpt7_ick = {
- .name = "gpt7_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpt7_ick_data,
-};
-
-static struct ti_clk_gate dss_tv_fck_data = {
- .parent = "omap_54m_fck",
- .bit_shift = 2,
- .reg = 0xe00,
- .module = TI_CLKM_CM,
-};
-
-static struct ti_clk dss_tv_fck = {
- .name = "dss_tv_fck",
- .clkdm_name = "dss_clkdm",
- .type = TI_CLK_GATE,
- .data = &dss_tv_fck_data,
-};
-
-static struct ti_clk_gate mcbsp5_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 10,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcbsp5_ick = {
- .name = "mcbsp5_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcbsp5_ick_data,
-};
-
-static struct ti_clk_gate mcspi1_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 18,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk mcspi1_ick = {
- .name = "mcspi1_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &mcspi1_ick_data,
-};
-
-static struct ti_clk_gate d2d_26m_fck_data = {
- .parent = "sys_ck",
- .bit_shift = 3,
- .reg = 0xa00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk d2d_26m_fck = {
- .name = "d2d_26m_fck",
- .clkdm_name = "d2d_clkdm",
- .type = TI_CLK_GATE,
- .data = &d2d_26m_fck_data,
-};
-
-static struct ti_clk_gate wdt3_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 12,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk wdt3_ick = {
- .name = "wdt3_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &wdt3_ick_data,
-};
-
-static struct ti_clk_divider pclkx2_fck_data = {
- .parent = "emu_src_ck",
- .bit_shift = 6,
- .max_div = 3,
- .reg = 0x1140,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_STARTS_AT_ONE,
-};
-
-static struct ti_clk pclkx2_fck = {
- .name = "pclkx2_fck",
- .type = TI_CLK_DIVIDER,
- .data = &pclkx2_fck_data,
-};
-
-static struct ti_clk_gate sha12_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 27,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk sha12_ick = {
- .name = "sha12_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &sha12_ick_data,
-};
-
-static struct ti_clk_gate emac_fck_data = {
- .parent = "rmii_ck",
- .bit_shift = 9,
- .reg = 0x59c,
- .module = TI_CLKM_SCRM,
-};
-
-static struct ti_clk emac_fck = {
- .name = "emac_fck",
- .type = TI_CLK_GATE,
- .data = &emac_fck_data,
-};
-
-static struct ti_clk_composite gpt10_fck_data = {
- .mux = &gpt10_mux_fck_data,
- .gate = &gpt10_gate_fck_data,
-};
-
-static struct ti_clk gpt10_fck = {
- .name = "gpt10_fck",
- .type = TI_CLK_COMPOSITE,
- .data = &gpt10_fck_data,
-};
-
-static struct ti_clk_gate wdt2_fck_data = {
- .parent = "wkup_32k_fck",
- .bit_shift = 5,
- .reg = 0xc00,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk wdt2_fck = {
- .name = "wdt2_fck",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &wdt2_fck_data,
-};
-
-static struct ti_clk_gate cam_ick_data = {
- .parent = "l4_ick",
- .bit_shift = 0,
- .reg = 0xf10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_NO_WAIT | CLKF_INTERFACE,
-};
-
-static struct ti_clk cam_ick = {
- .name = "cam_ick",
- .clkdm_name = "cam_clkdm",
- .type = TI_CLK_GATE,
- .data = &cam_ick_data,
-};
-
-static struct ti_clk_gate ssi_ick_3430es2_data = {
- .parent = "ssi_l4_ick",
- .bit_shift = 0,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_SSI | CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk ssi_ick_3430es2 = {
- .name = "ssi_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &ssi_ick_3430es2_data,
-};
-
-static struct ti_clk_gate gpio4_ick_data = {
- .parent = "per_l4_ick",
- .bit_shift = 15,
- .reg = 0x1010,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk gpio4_ick = {
- .name = "gpio4_ick",
- .clkdm_name = "per_clkdm",
- .type = TI_CLK_GATE,
- .data = &gpio4_ick_data,
-};
-
-static struct ti_clk_gate wdt1_ick_data = {
- .parent = "wkup_l4_ick",
- .bit_shift = 4,
- .reg = 0xc10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk wdt1_ick = {
- .name = "wdt1_ick",
- .clkdm_name = "wkup_clkdm",
- .type = TI_CLK_GATE,
- .data = &wdt1_ick_data,
-};
-
-static struct ti_clk_gate rng_ick_data = {
- .parent = "security_l4_ick2",
- .bit_shift = 2,
- .reg = 0xa14,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk rng_ick = {
- .name = "rng_ick",
- .type = TI_CLK_GATE,
- .data = &rng_ick_data,
-};
-
-static struct ti_clk_gate icr_ick_data = {
- .parent = "core_l4_ick",
- .bit_shift = 29,
- .reg = 0xa10,
- .module = TI_CLKM_CM,
- .flags = CLKF_OMAP3 | CLKF_INTERFACE,
-};
-
-static struct ti_clk icr_ick = {
- .name = "icr_ick",
- .clkdm_name = "core_l4_clkdm",
- .type = TI_CLK_GATE,
- .data = &icr_ick_data,
-};
-
-static struct ti_clk_gate sgx_ick_data = {
- .parent = "l3_ick",
- .bit_shift = 0,
- .reg = 0xb10,
- .module = TI_CLKM_CM,
- .flags = CLKF_WAIT,
-};
-
-static struct ti_clk sgx_ick = {
- .name = "sgx_ick",
- .clkdm_name = "sgx_clkdm",
- .type = TI_CLK_GATE,
- .data = &sgx_ick_data,
-};
-
-static struct ti_clk_divider sys_clkout2_data = {
- .parent = "clkout2_src_ck",
- .bit_shift = 3,
- .max_div = 64,
- .reg = 0xd70,
- .module = TI_CLKM_CM,
- .flags = CLKF_INDEX_POWER_OF_TWO,
-};
-
-static struct ti_clk sys_clkout2 = {
- .name = "sys_clkout2",
- .type = TI_CLK_DIVIDER,
- .data = &sys_clkout2_data,
-};
-
-static struct ti_clk_alias omap34xx_omap36xx_clks[] = {
- CLK(NULL, "security_l4_ick2", &security_l4_ick2),
- CLK(NULL, "aes1_ick", &aes1_ick),
- CLK("omap_rng", "ick", &rng_ick),
- CLK("omap3-rom-rng", "ick", &rng_ick),
- CLK(NULL, "sha11_ick", &sha11_ick),
- CLK(NULL, "des1_ick", &des1_ick),
- CLK(NULL, "cam_mclk", &cam_mclk),
- CLK(NULL, "cam_ick", &cam_ick),
- CLK(NULL, "csi2_96m_fck", &csi2_96m_fck),
- CLK(NULL, "security_l3_ick", &security_l3_ick),
- CLK(NULL, "pka_ick", &pka_ick),
- CLK(NULL, "icr_ick", &icr_ick),
- CLK(NULL, "des2_ick", &des2_ick),
- CLK(NULL, "mspro_ick", &mspro_ick),
- CLK(NULL, "mailboxes_ick", &mailboxes_ick),
- CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
- CLK(NULL, "sr1_fck", &sr1_fck),
- CLK(NULL, "sr2_fck", &sr2_fck),
- CLK(NULL, "sr_l4_ick", &sr_l4_ick),
- CLK(NULL, "dpll2_fck", &dpll2_fck),
- CLK(NULL, "dpll2_ck", &dpll2_ck),
- CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck),
- CLK(NULL, "iva2_ck", &iva2_ck),
- CLK(NULL, "modem_fck", &modem_fck),
- CLK(NULL, "sad2d_ick", &sad2d_ick),
- CLK(NULL, "mad2d_ick", &mad2d_ick),
- CLK(NULL, "mspro_fck", &mspro_fck),
- { NULL },
-};
-
-static struct ti_clk_alias omap36xx_omap3430es2plus_clks[] = {
- CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2),
- CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2),
- CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es2),
- CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es2),
- CLK(NULL, "ssi_ick", &ssi_ick_3430es2),
- CLK(NULL, "sys_d2_ck", &sys_d2_ck),
- CLK(NULL, "omap_96m_d2_fck", &omap_96m_d2_fck),
- CLK(NULL, "omap_96m_d4_fck", &omap_96m_d4_fck),
- CLK(NULL, "omap_96m_d8_fck", &omap_96m_d8_fck),
- CLK(NULL, "omap_96m_d10_fck", &omap_96m_d10_fck),
- CLK(NULL, "dpll5_m2_d4_ck", &dpll5_m2_d4_ck),
- CLK(NULL, "dpll5_m2_d8_ck", &dpll5_m2_d8_ck),
- CLK(NULL, "dpll5_m2_d16_ck", &dpll5_m2_d16_ck),
- CLK(NULL, "dpll5_m2_d20_ck", &dpll5_m2_d20_ck),
- CLK(NULL, "usim_fck", &usim_fck),
- CLK(NULL, "usim_ick", &usim_ick),
- { NULL },
-};
-
-static struct ti_clk_alias omap3xxx_clks[] = {
- CLK(NULL, "apb_pclk", &dummy_apb_pclk),
- CLK(NULL, "omap_32k_fck", &omap_32k_fck),
- CLK(NULL, "virt_12m_ck", &virt_12m_ck),
- CLK(NULL, "virt_13m_ck", &virt_13m_ck),
- CLK(NULL, "virt_19200000_ck", &virt_19200000_ck),
- CLK(NULL, "virt_26000000_ck", &virt_26000000_ck),
- CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck),
- CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck),
- CLK(NULL, "osc_sys_ck", &osc_sys_ck),
- CLK("twl", "fck", &osc_sys_ck),
- CLK(NULL, "sys_ck", &sys_ck),
- CLK(NULL, "timer_sys_ck", &sys_ck),
- CLK(NULL, "dpll4_ck", &dpll4_ck),
- CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck),
- CLK(NULL, "dpll4_m2x2_mul_ck", &dpll4_m2x2_mul_ck),
- CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck),
- CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck),
- CLK(NULL, "dpll3_ck", &dpll3_ck),
- CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck),
- CLK(NULL, "dpll3_m3x2_mul_ck", &dpll3_m3x2_mul_ck),
- CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck),
- CLK("etb", "emu_core_alwon_ck", &emu_core_alwon_ck),
- CLK(NULL, "sys_altclk", &sys_altclk),
- CLK(NULL, "sys_clkout1", &sys_clkout1),
- CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck),
- CLK(NULL, "core_ck", &core_ck),
- CLK(NULL, "dpll1_fck", &dpll1_fck),
- CLK(NULL, "dpll1_ck", &dpll1_ck),
- CLK(NULL, "cpufreq_ck", &dpll1_ck),
- CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck),
- CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck),
- CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck),
- CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck),
- CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck),
- CLK(NULL, "cm_96m_fck", &cm_96m_fck),
- CLK(NULL, "omap_96m_fck", &omap_96m_fck),
- CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck),
- CLK(NULL, "dpll4_m3x2_mul_ck", &dpll4_m3x2_mul_ck),
- CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck),
- CLK(NULL, "omap_54m_fck", &omap_54m_fck),
- CLK(NULL, "cm_96m_d2_fck", &cm_96m_d2_fck),
- CLK(NULL, "omap_48m_fck", &omap_48m_fck),
- CLK(NULL, "omap_12m_fck", &omap_12m_fck),
- CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck),
- CLK(NULL, "dpll4_m4x2_mul_ck", &dpll4_m4x2_mul_ck),
- CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck),
- CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck),
- CLK(NULL, "dpll4_m5x2_mul_ck", &dpll4_m5x2_mul_ck),
- CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck),
- CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck),
- CLK(NULL, "dpll4_m6x2_mul_ck", &dpll4_m6x2_mul_ck),
- CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck),
- CLK("etb", "emu_per_alwon_ck", &emu_per_alwon_ck),
- CLK(NULL, "clkout2_src_ck", &clkout2_src_ck),
- CLK(NULL, "sys_clkout2", &sys_clkout2),
- CLK(NULL, "corex2_fck", &corex2_fck),
- CLK(NULL, "mpu_ck", &mpu_ck),
- CLK(NULL, "arm_fck", &arm_fck),
- CLK("etb", "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
- CLK(NULL, "l3_ick", &l3_ick),
- CLK(NULL, "l4_ick", &l4_ick),
- CLK(NULL, "rm_ick", &rm_ick),
- CLK(NULL, "timer_32k_ck", &omap_32k_fck),
- CLK(NULL, "gpt10_fck", &gpt10_fck),
- CLK(NULL, "gpt11_fck", &gpt11_fck),
- CLK(NULL, "core_96m_fck", &core_96m_fck),
- CLK(NULL, "mmchs2_fck", &mmchs2_fck),
- CLK(NULL, "mmchs1_fck", &mmchs1_fck),
- CLK(NULL, "i2c3_fck", &i2c3_fck),
- CLK(NULL, "i2c2_fck", &i2c2_fck),
- CLK(NULL, "i2c1_fck", &i2c1_fck),
- CLK(NULL, "core_48m_fck", &core_48m_fck),
- CLK(NULL, "mcspi4_fck", &mcspi4_fck),
- CLK(NULL, "mcspi3_fck", &mcspi3_fck),
- CLK(NULL, "mcspi2_fck", &mcspi2_fck),
- CLK(NULL, "mcspi1_fck", &mcspi1_fck),
- CLK(NULL, "uart2_fck", &uart2_fck),
- CLK(NULL, "uart1_fck", &uart1_fck),
- CLK(NULL, "core_12m_fck", &core_12m_fck),
- CLK("omap_hdq.0", "fck", &hdq_fck),
- CLK(NULL, "hdq_fck", &hdq_fck),
- CLK(NULL, "core_l3_ick", &core_l3_ick),
- CLK(NULL, "sdrc_ick", &sdrc_ick),
- CLK(NULL, "gpmc_fck", &gpmc_fck),
- CLK(NULL, "core_l4_ick", &core_l4_ick),
- CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
- CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
- CLK(NULL, "mmchs2_ick", &mmchs2_ick),
- CLK(NULL, "mmchs1_ick", &mmchs1_ick),
- CLK("omap_hdq.0", "ick", &hdq_ick),
- CLK(NULL, "hdq_ick", &hdq_ick),
- CLK("omap2_mcspi.4", "ick", &mcspi4_ick),
- CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
- CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
- CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
- CLK(NULL, "mcspi4_ick", &mcspi4_ick),
- CLK(NULL, "mcspi3_ick", &mcspi3_ick),
- CLK(NULL, "mcspi2_ick", &mcspi2_ick),
- CLK(NULL, "mcspi1_ick", &mcspi1_ick),
- CLK("omap_i2c.3", "ick", &i2c3_ick),
- CLK("omap_i2c.2", "ick", &i2c2_ick),
- CLK("omap_i2c.1", "ick", &i2c1_ick),
- CLK(NULL, "i2c3_ick", &i2c3_ick),
- CLK(NULL, "i2c2_ick", &i2c2_ick),
- CLK(NULL, "i2c1_ick", &i2c1_ick),
- CLK(NULL, "uart2_ick", &uart2_ick),
- CLK(NULL, "uart1_ick", &uart1_ick),
- CLK(NULL, "gpt11_ick", &gpt11_ick),
- CLK(NULL, "gpt10_ick", &gpt10_ick),
- CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
- CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
- CLK(NULL, "omapctrl_ick", &omapctrl_ick),
- CLK(NULL, "dss_tv_fck", &dss_tv_fck),
- CLK(NULL, "dss_96m_fck", &dss_96m_fck),
- CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck),
- CLK(NULL, "init_60m_fclk", &dummy_ck),
- CLK(NULL, "gpt1_fck", &gpt1_fck),
- CLK(NULL, "aes2_ick", &aes2_ick),
- CLK(NULL, "wkup_32k_fck", &wkup_32k_fck),
- CLK(NULL, "gpio1_dbck", &gpio1_dbck),
- CLK(NULL, "sha12_ick", &sha12_ick),
- CLK(NULL, "wdt2_fck", &wdt2_fck),
- CLK(NULL, "wkup_l4_ick", &wkup_l4_ick),
- CLK("omap_wdt", "ick", &wdt2_ick),
- CLK(NULL, "wdt2_ick", &wdt2_ick),
- CLK(NULL, "wdt1_ick", &wdt1_ick),
- CLK(NULL, "gpio1_ick", &gpio1_ick),
- CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick),
- CLK(NULL, "gpt12_ick", &gpt12_ick),
- CLK(NULL, "gpt1_ick", &gpt1_ick),
- CLK(NULL, "per_96m_fck", &per_96m_fck),
- CLK(NULL, "per_48m_fck", &per_48m_fck),
- CLK(NULL, "uart3_fck", &uart3_fck),
- CLK(NULL, "gpt2_fck", &gpt2_fck),
- CLK(NULL, "gpt3_fck", &gpt3_fck),
- CLK(NULL, "gpt4_fck", &gpt4_fck),
- CLK(NULL, "gpt5_fck", &gpt5_fck),
- CLK(NULL, "gpt6_fck", &gpt6_fck),
- CLK(NULL, "gpt7_fck", &gpt7_fck),
- CLK(NULL, "gpt8_fck", &gpt8_fck),
- CLK(NULL, "gpt9_fck", &gpt9_fck),
- CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck),
- CLK(NULL, "gpio6_dbck", &gpio6_dbck),
- CLK(NULL, "gpio5_dbck", &gpio5_dbck),
- CLK(NULL, "gpio4_dbck", &gpio4_dbck),
- CLK(NULL, "gpio3_dbck", &gpio3_dbck),
- CLK(NULL, "gpio2_dbck", &gpio2_dbck),
- CLK(NULL, "wdt3_fck", &wdt3_fck),
- CLK(NULL, "per_l4_ick", &per_l4_ick),
- CLK(NULL, "gpio6_ick", &gpio6_ick),
- CLK(NULL, "gpio5_ick", &gpio5_ick),
- CLK(NULL, "gpio4_ick", &gpio4_ick),
- CLK(NULL, "gpio3_ick", &gpio3_ick),
- CLK(NULL, "gpio2_ick", &gpio2_ick),
- CLK(NULL, "wdt3_ick", &wdt3_ick),
- CLK(NULL, "uart3_ick", &uart3_ick),
- CLK(NULL, "uart4_ick", &uart4_ick),
- CLK(NULL, "gpt9_ick", &gpt9_ick),
- CLK(NULL, "gpt8_ick", &gpt8_ick),
- CLK(NULL, "gpt7_ick", &gpt7_ick),
- CLK(NULL, "gpt6_ick", &gpt6_ick),
- CLK(NULL, "gpt5_ick", &gpt5_ick),
- CLK(NULL, "gpt4_ick", &gpt4_ick),
- CLK(NULL, "gpt3_ick", &gpt3_ick),
- CLK(NULL, "gpt2_ick", &gpt2_ick),
- CLK(NULL, "mcbsp_clks", &mcbsp_clks),
- CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
- CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
- CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
- CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
- CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
- CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
- CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
- CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
- CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
- CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
- CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
- CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
- CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
- CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
- CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
- CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
- CLK("etb", "emu_src_ck", &emu_src_ck),
- CLK(NULL, "emu_src_mux_ck", &emu_src_mux_ck),
- CLK(NULL, "emu_src_ck", &emu_src_ck),
- CLK(NULL, "pclk_fck", &pclk_fck),
- CLK(NULL, "pclkx2_fck", &pclkx2_fck),
- CLK(NULL, "atclk_fck", &atclk_fck),
- CLK(NULL, "traceclk_src_fck", &traceclk_src_fck),
- CLK(NULL, "traceclk_fck", &traceclk_fck),
- CLK(NULL, "secure_32k_fck", &secure_32k_fck),
- CLK(NULL, "gpt12_fck", &gpt12_fck),
- CLK(NULL, "wdt1_fck", &wdt1_fck),
- { NULL },
-};
-
-static struct ti_clk_alias omap36xx_am35xx_omap3430es2plus_clks[] = {
- CLK(NULL, "dpll5_ck", &dpll5_ck),
- CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck),
- CLK(NULL, "core_d3_ck", &core_d3_ck),
- CLK(NULL, "core_d4_ck", &core_d4_ck),
- CLK(NULL, "core_d6_ck", &core_d6_ck),
- CLK(NULL, "omap_192m_alwon_fck", &omap_192m_alwon_fck),
- CLK(NULL, "core_d2_ck", &core_d2_ck),
- CLK(NULL, "corex2_d3_fck", &corex2_d3_fck),
- CLK(NULL, "corex2_d5_fck", &corex2_d5_fck),
- CLK(NULL, "sgx_fck", &sgx_fck),
- CLK(NULL, "sgx_ick", &sgx_ick),
- CLK(NULL, "cpefuse_fck", &cpefuse_fck),
- CLK(NULL, "ts_fck", &ts_fck),
- CLK(NULL, "usbtll_fck", &usbtll_fck),
- CLK(NULL, "usbtll_ick", &usbtll_ick),
- CLK("omap_hsmmc.2", "ick", &mmchs3_ick),
- CLK(NULL, "mmchs3_ick", &mmchs3_ick),
- CLK(NULL, "mmchs3_fck", &mmchs3_fck),
- CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2),
- CLK("omapdss_dss", "ick", &dss_ick_3430es2),
- CLK(NULL, "dss_ick", &dss_ick_3430es2),
- CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck),
- CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck),
- CLK(NULL, "usbhost_ick", &usbhost_ick),
- { NULL },
-};
-
-static struct ti_clk_alias omap3430es1_clks[] = {
- CLK(NULL, "gfx_l3_ck", &gfx_l3_ck),
- CLK(NULL, "gfx_l3_fck", &gfx_l3_fck),
- CLK(NULL, "gfx_l3_ick", &gfx_l3_ick),
- CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck),
- CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck),
- CLK(NULL, "d2d_26m_fck", &d2d_26m_fck),
- CLK(NULL, "fshostusb_fck", &fshostusb_fck),
- CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1),
- CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1),
- CLK("musb-omap2430", "ick", &hsotgusb_ick_3430es1),
- CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_3430es1),
- CLK(NULL, "fac_ick", &fac_ick),
- CLK(NULL, "ssi_ick", &ssi_ick_3430es1),
- CLK(NULL, "usb_l4_ick", &usb_l4_ick),
- CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1),
- CLK("omapdss_dss", "ick", &dss_ick_3430es1),
- CLK(NULL, "dss_ick", &dss_ick_3430es1),
- { NULL },
-};
-
-static struct ti_clk_alias omap36xx_clks[] = {
- CLK(NULL, "uart4_fck", &uart4_fck),
- { NULL },
-};
-
-static struct ti_clk_alias am35xx_clks[] = {
- CLK(NULL, "ipss_ick", &ipss_ick),
- CLK(NULL, "rmii_ck", &rmii_ck),
- CLK(NULL, "pclk_ck", &pclk_ck),
- CLK(NULL, "emac_ick", &emac_ick),
- CLK(NULL, "emac_fck", &emac_fck),
- CLK("davinci_emac.0", NULL, &emac_ick),
- CLK("davinci_mdio.0", NULL, &emac_fck),
- CLK("vpfe-capture", "master", &vpfe_ick),
- CLK("vpfe-capture", "slave", &vpfe_fck),
- CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx),
- CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx),
- CLK(NULL, "hecc_ck", &hecc_ck),
- CLK(NULL, "uart4_ick", &uart4_ick_am35xx),
- CLK(NULL, "uart4_fck", &uart4_fck_am35xx),
- { NULL },
-};
-
-static struct ti_clk *omap36xx_clk_patches[] = {
- &dpll4_m3x2_ck_omap36xx,
- &dpll3_m3x2_ck_omap36xx,
- &dpll4_m6x2_ck_omap36xx,
- &dpll4_m2x2_ck_omap36xx,
- &dpll4_m5x2_ck_omap36xx,
- &dpll4_ck_omap36xx,
- NULL,
-};
-
-static const char *enable_init_clks[] = {
- "sdrc_ick",
- "gpmc_fck",
- "omapctrl_ick",
-};
-
-static void __init omap3_clk_legacy_common_init(void)
-{
- omap2_clk_disable_autoidle_all();
-
- omap2_clk_enable_init_clocks(enable_init_clks,
- ARRAY_SIZE(enable_init_clks));
-
- pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
- (clk_get_rate(osc_sys_ck.clk) / 1000000),
- (clk_get_rate(osc_sys_ck.clk) / 100000) % 10,
- (clk_get_rate(core_ck.clk) / 1000000),
- (clk_get_rate(arm_fck.clk) / 1000000));
-}
-
-int __init omap3430es1_clk_legacy_init(void)
-{
- int r;
-
- r = ti_clk_register_legacy_clks(omap3430es1_clks);
- r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
- r |= ti_clk_register_legacy_clks(omap3xxx_clks);
-
- omap3_clk_legacy_common_init();
-
- return r;
-}
-
-int __init omap3430_clk_legacy_init(void)
-{
- int r;
-
- r = ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
- r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
- r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
- r |= ti_clk_register_legacy_clks(omap3xxx_clks);
-
- omap3_clk_legacy_common_init();
- omap3_clk_lock_dpll5();
-
- return r;
-}
-
-int __init omap36xx_clk_legacy_init(void)
-{
- int r;
-
- ti_clk_patch_legacy_clks(omap36xx_clk_patches);
- r = ti_clk_register_legacy_clks(omap36xx_clks);
- r |= ti_clk_register_legacy_clks(omap36xx_omap3430es2plus_clks);
- r |= ti_clk_register_legacy_clks(omap34xx_omap36xx_clks);
- r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
- r |= ti_clk_register_legacy_clks(omap3xxx_clks);
-
- omap3_clk_legacy_common_init();
- omap3_clk_lock_dpll5();
-
- return r;
-}
-
-int __init am35xx_clk_legacy_init(void)
-{
- int r;
-
- r = ti_clk_register_legacy_clks(am35xx_clks);
- r |= ti_clk_register_legacy_clks(omap36xx_am35xx_omap3430es2plus_clks);
- r |= ti_clk_register_legacy_clks(omap3xxx_clks);
-
- omap3_clk_legacy_common_init();
- omap3_clk_lock_dpll5();
-
- return r;
-}
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index b1251ca..8aa5f57 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -224,296 +224,43 @@ const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait = {
};
static struct ti_dt_clk omap3xxx_clks[] = {
- DT_CLK(NULL, "apb_pclk", "dummy_apb_pclk"),
- DT_CLK(NULL, "omap_32k_fck", "omap_32k_fck"),
- DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"),
- DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_38_4m_ck", "virt_38_4m_ck"),
- DT_CLK(NULL, "osc_sys_ck", "osc_sys_ck"),
- DT_CLK("twl", "fck", "osc_sys_ck"),
- DT_CLK(NULL, "sys_ck", "sys_ck"),
- DT_CLK(NULL, "omap_96m_alwon_fck", "omap_96m_alwon_fck"),
- DT_CLK("etb", "emu_core_alwon_ck", "emu_core_alwon_ck"),
- DT_CLK(NULL, "sys_altclk", "sys_altclk"),
- DT_CLK(NULL, "sys_clkout1", "sys_clkout1"),
- DT_CLK(NULL, "dpll1_ck", "dpll1_ck"),
- DT_CLK(NULL, "dpll1_x2_ck", "dpll1_x2_ck"),
- DT_CLK(NULL, "dpll1_x2m2_ck", "dpll1_x2m2_ck"),
- DT_CLK(NULL, "dpll3_ck", "dpll3_ck"),
- DT_CLK(NULL, "core_ck", "core_ck"),
- DT_CLK(NULL, "dpll3_x2_ck", "dpll3_x2_ck"),
- DT_CLK(NULL, "dpll3_m2_ck", "dpll3_m2_ck"),
- DT_CLK(NULL, "dpll3_m2x2_ck", "dpll3_m2x2_ck"),
- DT_CLK(NULL, "dpll3_m3_ck", "dpll3_m3_ck"),
- DT_CLK(NULL, "dpll3_m3x2_ck", "dpll3_m3x2_ck"),
- DT_CLK(NULL, "dpll4_ck", "dpll4_ck"),
- DT_CLK(NULL, "dpll4_x2_ck", "dpll4_x2_ck"),
- DT_CLK(NULL, "omap_96m_fck", "omap_96m_fck"),
- DT_CLK(NULL, "cm_96m_fck", "cm_96m_fck"),
- DT_CLK(NULL, "omap_54m_fck", "omap_54m_fck"),
- DT_CLK(NULL, "omap_48m_fck", "omap_48m_fck"),
- DT_CLK(NULL, "omap_12m_fck", "omap_12m_fck"),
- DT_CLK(NULL, "dpll4_m2_ck", "dpll4_m2_ck"),
- DT_CLK(NULL, "dpll4_m2x2_ck", "dpll4_m2x2_ck"),
- DT_CLK(NULL, "dpll4_m3_ck", "dpll4_m3_ck"),
- DT_CLK(NULL, "dpll4_m3x2_ck", "dpll4_m3x2_ck"),
- DT_CLK(NULL, "dpll4_m4_ck", "dpll4_m4_ck"),
- DT_CLK(NULL, "dpll4_m4x2_ck", "dpll4_m4x2_ck"),
- DT_CLK(NULL, "dpll4_m5_ck", "dpll4_m5_ck"),
- DT_CLK(NULL, "dpll4_m5x2_ck", "dpll4_m5x2_ck"),
- DT_CLK(NULL, "dpll4_m6_ck", "dpll4_m6_ck"),
- DT_CLK(NULL, "dpll4_m6x2_ck", "dpll4_m6x2_ck"),
- DT_CLK("etb", "emu_per_alwon_ck", "emu_per_alwon_ck"),
- DT_CLK(NULL, "clkout2_src_ck", "clkout2_src_ck"),
- DT_CLK(NULL, "sys_clkout2", "sys_clkout2"),
- DT_CLK(NULL, "corex2_fck", "corex2_fck"),
- DT_CLK(NULL, "dpll1_fck", "dpll1_fck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "arm_fck", "arm_fck"),
- DT_CLK("etb", "emu_mpu_alwon_ck", "emu_mpu_alwon_ck"),
- DT_CLK(NULL, "l3_ick", "l3_ick"),
- DT_CLK(NULL, "l4_ick", "l4_ick"),
- DT_CLK(NULL, "rm_ick", "rm_ick"),
- DT_CLK(NULL, "gpt10_fck", "gpt10_fck"),
- DT_CLK(NULL, "gpt11_fck", "gpt11_fck"),
- DT_CLK(NULL, "core_96m_fck", "core_96m_fck"),
- DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"),
- DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"),
- DT_CLK(NULL, "i2c3_fck", "i2c3_fck"),
- DT_CLK(NULL, "i2c2_fck", "i2c2_fck"),
- DT_CLK(NULL, "i2c1_fck", "i2c1_fck"),
- DT_CLK(NULL, "core_48m_fck", "core_48m_fck"),
- DT_CLK(NULL, "mcspi4_fck", "mcspi4_fck"),
- DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"),
- DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"),
- DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"),
- DT_CLK(NULL, "uart2_fck", "uart2_fck"),
- DT_CLK(NULL, "uart1_fck", "uart1_fck"),
- DT_CLK(NULL, "core_12m_fck", "core_12m_fck"),
- DT_CLK("omap_hdq.0", "fck", "hdq_fck"),
- DT_CLK(NULL, "hdq_fck", "hdq_fck"),
- DT_CLK(NULL, "core_l3_ick", "core_l3_ick"),
- DT_CLK(NULL, "sdrc_ick", "sdrc_ick"),
- DT_CLK(NULL, "gpmc_fck", "gpmc_fck"),
- DT_CLK(NULL, "core_l4_ick", "core_l4_ick"),
- DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"),
- DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"),
- DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"),
- DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"),
- DT_CLK("omap_hdq.0", "ick", "hdq_ick"),
- DT_CLK(NULL, "hdq_ick", "hdq_ick"),
- DT_CLK("omap2_mcspi.4", "ick", "mcspi4_ick"),
- DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"),
- DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"),
- DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"),
- DT_CLK(NULL, "mcspi4_ick", "mcspi4_ick"),
- DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"),
- DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"),
- DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"),
- DT_CLK("omap_i2c.3", "ick", "i2c3_ick"),
- DT_CLK("omap_i2c.2", "ick", "i2c2_ick"),
- DT_CLK("omap_i2c.1", "ick", "i2c1_ick"),
- DT_CLK(NULL, "i2c3_ick", "i2c3_ick"),
- DT_CLK(NULL, "i2c2_ick", "i2c2_ick"),
- DT_CLK(NULL, "i2c1_ick", "i2c1_ick"),
- DT_CLK(NULL, "uart2_ick", "uart2_ick"),
- DT_CLK(NULL, "uart1_ick", "uart1_ick"),
- DT_CLK(NULL, "gpt11_ick", "gpt11_ick"),
- DT_CLK(NULL, "gpt10_ick", "gpt10_ick"),
- DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"),
- DT_CLK(NULL, "dss_tv_fck", "dss_tv_fck"),
- DT_CLK(NULL, "dss_96m_fck", "dss_96m_fck"),
- DT_CLK(NULL, "dss2_alwon_fck", "dss2_alwon_fck"),
- DT_CLK(NULL, "init_60m_fclk", "dummy_ck"),
- DT_CLK(NULL, "gpt1_fck", "gpt1_fck"),
- DT_CLK(NULL, "aes2_ick", "aes2_ick"),
- DT_CLK(NULL, "wkup_32k_fck", "wkup_32k_fck"),
- DT_CLK(NULL, "gpio1_dbck", "gpio1_dbck"),
- DT_CLK(NULL, "sha12_ick", "sha12_ick"),
- DT_CLK(NULL, "wdt2_fck", "wdt2_fck"),
- DT_CLK("omap_wdt", "ick", "wdt2_ick"),
- DT_CLK(NULL, "wdt2_ick", "wdt2_ick"),
- DT_CLK(NULL, "wdt1_ick", "wdt1_ick"),
- DT_CLK(NULL, "gpio1_ick", "gpio1_ick"),
- DT_CLK(NULL, "omap_32ksync_ick", "omap_32ksync_ick"),
- DT_CLK(NULL, "gpt12_ick", "gpt12_ick"),
- DT_CLK(NULL, "gpt1_ick", "gpt1_ick"),
- DT_CLK(NULL, "per_96m_fck", "per_96m_fck"),
- DT_CLK(NULL, "per_48m_fck", "per_48m_fck"),
- DT_CLK(NULL, "uart3_fck", "uart3_fck"),
- DT_CLK(NULL, "gpt2_fck", "gpt2_fck"),
- DT_CLK(NULL, "gpt3_fck", "gpt3_fck"),
- DT_CLK(NULL, "gpt4_fck", "gpt4_fck"),
- DT_CLK(NULL, "gpt5_fck", "gpt5_fck"),
- DT_CLK(NULL, "gpt6_fck", "gpt6_fck"),
- DT_CLK(NULL, "gpt7_fck", "gpt7_fck"),
- DT_CLK(NULL, "gpt8_fck", "gpt8_fck"),
- DT_CLK(NULL, "gpt9_fck", "gpt9_fck"),
- DT_CLK(NULL, "per_32k_alwon_fck", "per_32k_alwon_fck"),
- DT_CLK(NULL, "gpio6_dbck", "gpio6_dbck"),
- DT_CLK(NULL, "gpio5_dbck", "gpio5_dbck"),
- DT_CLK(NULL, "gpio4_dbck", "gpio4_dbck"),
- DT_CLK(NULL, "gpio3_dbck", "gpio3_dbck"),
- DT_CLK(NULL, "gpio2_dbck", "gpio2_dbck"),
- DT_CLK(NULL, "wdt3_fck", "wdt3_fck"),
- DT_CLK(NULL, "per_l4_ick", "per_l4_ick"),
- DT_CLK(NULL, "gpio6_ick", "gpio6_ick"),
- DT_CLK(NULL, "gpio5_ick", "gpio5_ick"),
- DT_CLK(NULL, "gpio4_ick", "gpio4_ick"),
- DT_CLK(NULL, "gpio3_ick", "gpio3_ick"),
- DT_CLK(NULL, "gpio2_ick", "gpio2_ick"),
- DT_CLK(NULL, "wdt3_ick", "wdt3_ick"),
- DT_CLK(NULL, "uart3_ick", "uart3_ick"),
- DT_CLK(NULL, "gpt9_ick", "gpt9_ick"),
- DT_CLK(NULL, "gpt8_ick", "gpt8_ick"),
- DT_CLK(NULL, "gpt7_ick", "gpt7_ick"),
- DT_CLK(NULL, "gpt6_ick", "gpt6_ick"),
- DT_CLK(NULL, "gpt5_ick", "gpt5_ick"),
- DT_CLK(NULL, "gpt4_ick", "gpt4_ick"),
- DT_CLK(NULL, "gpt3_ick", "gpt3_ick"),
- DT_CLK(NULL, "gpt2_ick", "gpt2_ick"),
- DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"),
- DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"),
- DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"),
- DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"),
- DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"),
- DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"),
- DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"),
- DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"),
- DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"),
- DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"),
- DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"),
- DT_CLK("etb", "emu_src_ck", "emu_src_ck"),
- DT_CLK(NULL, "emu_src_ck", "emu_src_ck"),
- DT_CLK(NULL, "pclk_fck", "pclk_fck"),
- DT_CLK(NULL, "pclkx2_fck", "pclkx2_fck"),
- DT_CLK(NULL, "atclk_fck", "atclk_fck"),
- DT_CLK(NULL, "traceclk_src_fck", "traceclk_src_fck"),
- DT_CLK(NULL, "traceclk_fck", "traceclk_fck"),
- DT_CLK(NULL, "secure_32k_fck", "secure_32k_fck"),
- DT_CLK(NULL, "gpt12_fck", "gpt12_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
DT_CLK(NULL, "timer_32k_ck", "omap_32k_fck"),
DT_CLK(NULL, "timer_sys_ck", "sys_ck"),
- DT_CLK(NULL, "cpufreq_ck", "dpll1_ck"),
- { .node_name = NULL },
-};
-
-static struct ti_dt_clk omap34xx_omap36xx_clks[] = {
- DT_CLK(NULL, "aes1_ick", "aes1_ick"),
- DT_CLK("omap_rng", "ick", "rng_ick"),
- DT_CLK("omap3-rom-rng", "ick", "rng_ick"),
- DT_CLK(NULL, "sha11_ick", "sha11_ick"),
- DT_CLK(NULL, "des1_ick", "des1_ick"),
- DT_CLK(NULL, "cam_mclk", "cam_mclk"),
- DT_CLK(NULL, "cam_ick", "cam_ick"),
- DT_CLK(NULL, "csi2_96m_fck", "csi2_96m_fck"),
- DT_CLK(NULL, "security_l3_ick", "security_l3_ick"),
- DT_CLK(NULL, "pka_ick", "pka_ick"),
- DT_CLK(NULL, "icr_ick", "icr_ick"),
- DT_CLK("omap-aes", "ick", "aes2_ick"),
- DT_CLK("omap-sham", "ick", "sha12_ick"),
- DT_CLK(NULL, "des2_ick", "des2_ick"),
- DT_CLK(NULL, "mspro_ick", "mspro_ick"),
- DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"),
- DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"),
- DT_CLK(NULL, "sr1_fck", "sr1_fck"),
- DT_CLK(NULL, "sr2_fck", "sr2_fck"),
- DT_CLK(NULL, "sr_l4_ick", "sr_l4_ick"),
- DT_CLK(NULL, "security_l4_ick2", "security_l4_ick2"),
- DT_CLK(NULL, "wkup_l4_ick", "wkup_l4_ick"),
- DT_CLK(NULL, "dpll2_fck", "dpll2_fck"),
- DT_CLK(NULL, "iva2_ck", "iva2_ck"),
- DT_CLK(NULL, "modem_fck", "modem_fck"),
- DT_CLK(NULL, "sad2d_ick", "sad2d_ick"),
- DT_CLK(NULL, "mad2d_ick", "mad2d_ick"),
- DT_CLK(NULL, "mspro_fck", "mspro_fck"),
- DT_CLK(NULL, "dpll2_ck", "dpll2_ck"),
- DT_CLK(NULL, "dpll2_m2_ck", "dpll2_m2_ck"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap36xx_omap3430es2plus_clks[] = {
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es2"),
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es2"),
- DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es2"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es2"),
- DT_CLK(NULL, "usim_fck", "usim_fck"),
- DT_CLK(NULL, "usim_ick", "usim_ick"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap3430es1_clks[] = {
- DT_CLK(NULL, "gfx_l3_ck", "gfx_l3_ck"),
- DT_CLK(NULL, "gfx_l3_fck", "gfx_l3_fck"),
- DT_CLK(NULL, "gfx_l3_ick", "gfx_l3_ick"),
- DT_CLK(NULL, "gfx_cg1_ck", "gfx_cg1_ck"),
- DT_CLK(NULL, "gfx_cg2_ck", "gfx_cg2_ck"),
- DT_CLK(NULL, "d2d_26m_fck", "d2d_26m_fck"),
- DT_CLK(NULL, "fshostusb_fck", "fshostusb_fck"),
DT_CLK(NULL, "ssi_ssr_fck", "ssi_ssr_fck_3430es1"),
DT_CLK(NULL, "ssi_sst_fck", "ssi_sst_fck_3430es1"),
- DT_CLK("musb-omap2430", "ick", "hsotgusb_ick_3430es1"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_3430es1"),
- DT_CLK(NULL, "fac_ick", "fac_ick"),
DT_CLK(NULL, "ssi_ick", "ssi_ick_3430es1"),
- DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es1"),
- DT_CLK("omapdss_dss", "ick", "dss_ick_3430es1"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es1"),
{ .node_name = NULL },
};
static struct ti_dt_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
- DT_CLK(NULL, "virt_16_8m_ck", "virt_16_8m_ck"),
- DT_CLK(NULL, "dpll5_ck", "dpll5_ck"),
- DT_CLK(NULL, "dpll5_m2_ck", "dpll5_m2_ck"),
- DT_CLK(NULL, "sgx_fck", "sgx_fck"),
- DT_CLK(NULL, "sgx_ick", "sgx_ick"),
- DT_CLK(NULL, "cpefuse_fck", "cpefuse_fck"),
- DT_CLK(NULL, "ts_fck", "ts_fck"),
- DT_CLK(NULL, "usbtll_fck", "usbtll_fck"),
- DT_CLK(NULL, "usbtll_ick", "usbtll_ick"),
- DT_CLK("omap_hsmmc.2", "ick", "mmchs3_ick"),
- DT_CLK(NULL, "mmchs3_ick", "mmchs3_ick"),
- DT_CLK(NULL, "mmchs3_fck", "mmchs3_fck"),
DT_CLK(NULL, "dss1_alwon_fck", "dss1_alwon_fck_3430es2"),
- DT_CLK("omapdss_dss", "ick", "dss_ick_3430es2"),
DT_CLK(NULL, "dss_ick", "dss_ick_3430es2"),
- DT_CLK(NULL, "usbhost_120m_fck", "usbhost_120m_fck"),
- DT_CLK(NULL, "usbhost_48m_fck", "usbhost_48m_fck"),
- DT_CLK(NULL, "usbhost_ick", "usbhost_ick"),
{ .node_name = NULL },
};
static struct ti_dt_clk am35xx_clks[] = {
- DT_CLK(NULL, "ipss_ick", "ipss_ick"),
- DT_CLK(NULL, "rmii_ck", "rmii_ck"),
- DT_CLK(NULL, "pclk_ck", "pclk_ck"),
- DT_CLK(NULL, "emac_ick", "emac_ick"),
- DT_CLK(NULL, "emac_fck", "emac_fck"),
- DT_CLK("davinci_emac.0", NULL, "emac_ick"),
- DT_CLK("davinci_mdio.0", NULL, "emac_fck"),
- DT_CLK("vpfe-capture", "master", "vpfe_ick"),
- DT_CLK("vpfe-capture", "slave", "vpfe_fck"),
DT_CLK(NULL, "hsotgusb_ick", "hsotgusb_ick_am35xx"),
DT_CLK(NULL, "hsotgusb_fck", "hsotgusb_fck_am35xx"),
- DT_CLK(NULL, "hecc_ck", "hecc_ck"),
DT_CLK(NULL, "uart4_ick", "uart4_ick_am35xx"),
DT_CLK(NULL, "uart4_fck", "uart4_fck_am35xx"),
{ .node_name = NULL },
};
-static struct ti_dt_clk omap36xx_clks[] = {
- DT_CLK(NULL, "omap_192m_alwon_fck", "omap_192m_alwon_fck"),
- DT_CLK(NULL, "uart4_fck", "uart4_fck"),
- DT_CLK(NULL, "uart4_ick", "uart4_ick"),
- { .node_name = NULL },
-};
-
static const char *enable_init_clks[] = {
"sdrc_ick",
"gpmc_fck",
@@ -579,16 +326,10 @@ static int __init omap3xxx_dt_clk_init(int soc_type)
soc_type == OMAP3_SOC_OMAP3630)
ti_dt_clocks_register(omap36xx_omap3430es2plus_clks);
- if (soc_type == OMAP3_SOC_OMAP3430_ES1 ||
- soc_type == OMAP3_SOC_OMAP3430_ES2_PLUS ||
- soc_type == OMAP3_SOC_OMAP3630)
- ti_dt_clocks_register(omap34xx_omap36xx_clks);
-
- if (soc_type == OMAP3_SOC_OMAP3630)
- ti_dt_clocks_register(omap36xx_clks);
-
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
+
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index e816a75..2b7c2e0 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -19,109 +19,208 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
+#include <dt-bindings/clock/am4.h>
#include "clock.h"
+static const char * const am4_synctimer_32kclk_parents[] __initconst = {
+ "mux_synctimer32k_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am4_counter_32k_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_synctimer_32kclk_parents, NULL },
+ { 0 },
+};
+
+static const char * const am4_gpio0_dbclk_parents[] __initconst = {
+ "gpio0_dbclk_mux_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio0_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am4_l4_wkup_clkctrl_regs[] __initconst = {
+ { AM4_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck", "l3s_tsc_clkdm" },
+ { AM4_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
+ { AM4_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "sys_clkin_ck" },
+ { AM4_COUNTER_32K_CLKCTRL, am4_counter_32k_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0210:8" },
+ { AM4_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck", "l4_wkup_clkdm" },
+ { AM4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck", "l4_wkup_clkdm" },
+ { AM4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
+ { AM4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck", "l4_wkup_clkdm" },
+ { AM4_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck", "l4_wkup_clkdm" },
+ { AM4_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck", "l4_wkup_clkdm" },
+ { AM4_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
+ { AM4_GPIO1_CLKCTRL, am4_gpio1_bit_data, CLKF_SW_SUP, "sys_clkin_ck", "l4_wkup_clkdm" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am4_mpu_clkctrl_regs[] __initconst = {
+ { AM4_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am4_gfx_l3_clkctrl_regs[] __initconst = {
+ { AM4_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am4_l4_rtc_clkctrl_regs[] __initconst = {
+ { AM4_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
+ { 0 },
+};
+
+static const char * const am4_usb_otg_ss0_refclk960m_parents[] __initconst = {
+ "dpll_per_clkdcoldo",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am4_usb_otg_ss0_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am4_usb_otg_ss1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_usb_otg_ss0_refclk960m_parents, NULL },
+ { 0 },
+};
+
+static const char * const am4_gpio1_dbclk_parents[] __initconst = {
+ "clkdiv32k_ick",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio3_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio4_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio5_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data am4_gpio6_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, am4_gpio1_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data am4_l4_per_clkctrl_regs[] __initconst = {
+ { AM4_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
+ { AM4_DES_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_VPFE0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
+ { AM4_VPFE1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3s_clkdm" },
+ { AM4_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
+ { AM4_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l3_clkdm" },
+ { AM4_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
+ { AM4_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
+ { AM4_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
+ { AM4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
+ { AM4_QSPI_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
+ { AM4_USB_OTG_SS0_CLKCTRL, am4_usb_otg_ss0_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
+ { AM4_USB_OTG_SS1_CLKCTRL, am4_usb_otg_ss1_bit_data, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
+ { AM4_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
+ { AM4_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
+ { AM4_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
+ { AM4_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EPWMSS3_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EPWMSS4_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EPWMSS5_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_GPIO2_CLKCTRL, am4_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_GPIO3_CLKCTRL, am4_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_GPIO4_CLKCTRL, am4_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_GPIO5_CLKCTRL, am4_gpio5_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_GPIO6_CLKCTRL, am4_gpio6_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_clk" },
+ { AM4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
+ { AM4_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
+ { AM4_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
+ { AM4_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_SPI2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_SPI3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_SPI4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
+ { AM4_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
+ { AM4_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
+ { AM4_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
+ { AM4_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
+ { AM4_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
+ { AM4_TIMER8_CLKCTRL, NULL, CLKF_SW_SUP, "timer8_fck" },
+ { AM4_TIMER9_CLKCTRL, NULL, CLKF_SW_SUP, "timer9_fck" },
+ { AM4_TIMER10_CLKCTRL, NULL, CLKF_SW_SUP, "timer10_fck" },
+ { AM4_TIMER11_CLKCTRL, NULL, CLKF_SW_SUP, "timer11_fck" },
+ { AM4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
+ { AM4_OCP2SCP0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_OCP2SCP1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
+ { AM4_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_ck", "emif_clkdm" },
+ { AM4_DSS_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "disp_clk", "dss_clkdm" },
+ { AM4_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data am4_clkctrl_data[] __initconst = {
+ { 0x44df2820, am4_l4_wkup_clkctrl_regs },
+ { 0x44df8320, am4_mpu_clkctrl_regs },
+ { 0x44df8420, am4_gfx_l3_clkctrl_regs },
+ { 0x44df8520, am4_l4_rtc_clkctrl_regs },
+ { 0x44df8820, am4_l4_per_clkctrl_regs },
+ { 0 },
+};
+
+const struct omap_clkctrl_data am438x_clkctrl_data[] __initconst = {
+ { 0x44df2820, am4_l4_wkup_clkctrl_regs },
+ { 0x44df8320, am4_mpu_clkctrl_regs },
+ { 0x44df8420, am4_gfx_l3_clkctrl_regs },
+ { 0x44df8820, am4_l4_per_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk am43xx_clks[] = {
- DT_CLK(NULL, "clk_32768_ck", "clk_32768_ck"),
- DT_CLK(NULL, "clk_rc32k_ck", "clk_rc32k_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_24000000_ck", "virt_24000000_ck"),
- DT_CLK(NULL, "virt_25000000_ck", "virt_25000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "tclkin_ck", "tclkin_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_m4_ck", "dpll_core_m4_ck"),
- DT_CLK(NULL, "dpll_core_m5_ck", "dpll_core_m5_ck"),
- DT_CLK(NULL, "dpll_core_m6_ck", "dpll_core_m6_ck"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "dpll_disp_ck", "dpll_disp_ck"),
- DT_CLK(NULL, "dpll_disp_m2_ck", "dpll_disp_m2_ck"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_wkupdm_ck", "dpll_per_m2_div4_wkupdm_ck"),
- DT_CLK(NULL, "dpll_per_m2_div4_ck", "dpll_per_m2_div4_ck"),
- DT_CLK(NULL, "adc_tsc_fck", "adc_tsc_fck"),
- DT_CLK(NULL, "clkdiv32k_ck", "clkdiv32k_ck"),
- DT_CLK(NULL, "clkdiv32k_ick", "clkdiv32k_ick"),
- DT_CLK(NULL, "dcan0_fck", "dcan0_fck"),
- DT_CLK(NULL, "dcan1_fck", "dcan1_fck"),
- DT_CLK(NULL, "pruss_ocp_gclk", "pruss_ocp_gclk"),
- DT_CLK(NULL, "mcasp0_fck", "mcasp0_fck"),
- DT_CLK(NULL, "mcasp1_fck", "mcasp1_fck"),
- DT_CLK(NULL, "smartreflex0_fck", "smartreflex0_fck"),
- DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
- DT_CLK(NULL, "sha0_fck", "sha0_fck"),
- DT_CLK(NULL, "aes0_fck", "aes0_fck"),
- DT_CLK(NULL, "rng_fck", "rng_fck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "wdt1_fck", "wdt1_fck"),
- DT_CLK(NULL, "l3_gclk", "l3_gclk"),
- DT_CLK(NULL, "dpll_core_m4_div2_ck", "dpll_core_m4_div2_ck"),
- DT_CLK(NULL, "l4hs_gclk", "l4hs_gclk"),
- DT_CLK(NULL, "l3s_gclk", "l3s_gclk"),
- DT_CLK(NULL, "l4ls_gclk", "l4ls_gclk"),
- DT_CLK(NULL, "clk_24mhz", "clk_24mhz"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
- DT_CLK(NULL, "dpll_clksel_mac_clk", "dpll_clksel_mac_clk"),
- DT_CLK(NULL, "gpio0_dbclk_mux_ck", "gpio0_dbclk_mux_ck"),
- DT_CLK(NULL, "gpio0_dbclk", "gpio0_dbclk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "mmc_clk", "mmc_clk"),
- DT_CLK(NULL, "gfx_fclk_clksel_ck", "gfx_fclk_clksel_ck"),
- DT_CLK(NULL, "gfx_fck_div_ck", "gfx_fck_div_ck"),
DT_CLK(NULL, "timer_32k_ck", "clkdiv32k_ick"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "sysclk_div", "sysclk_div"),
- DT_CLK(NULL, "disp_clk", "disp_clk"),
- DT_CLK(NULL, "clk_32k_mosc_ck", "clk_32k_mosc_ck"),
- DT_CLK(NULL, "clk_32k_tpm_ck", "clk_32k_tpm_ck"),
- DT_CLK(NULL, "dpll_extdev_ck", "dpll_extdev_ck"),
- DT_CLK(NULL, "dpll_extdev_m2_ck", "dpll_extdev_m2_ck"),
- DT_CLK(NULL, "mux_synctimer32k_ck", "mux_synctimer32k_ck"),
- DT_CLK(NULL, "synctimer_32kclk", "synctimer_32kclk"),
- DT_CLK(NULL, "timer8_fck", "timer8_fck"),
- DT_CLK(NULL, "timer9_fck", "timer9_fck"),
- DT_CLK(NULL, "timer10_fck", "timer10_fck"),
- DT_CLK(NULL, "timer11_fck", "timer11_fck"),
- DT_CLK(NULL, "cpsw_50m_clkdiv", "cpsw_50m_clkdiv"),
- DT_CLK(NULL, "cpsw_5m_clkdiv", "cpsw_5m_clkdiv"),
- DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
- DT_CLK(NULL, "dpll_ddr_m4_ck", "dpll_ddr_m4_ck"),
- DT_CLK(NULL, "dpll_per_clkdcoldo", "dpll_per_clkdcoldo"),
- DT_CLK(NULL, "dll_aging_clk_div", "dll_aging_clk_div"),
- DT_CLK(NULL, "div_core_25m_ck", "div_core_25m_ck"),
- DT_CLK(NULL, "func_12m_clk", "func_12m_clk"),
- DT_CLK(NULL, "vtp_clk_div", "vtp_clk_div"),
- DT_CLK(NULL, "usbphy_32khz_clkmux", "usbphy_32khz_clkmux"),
- DT_CLK("48300200.ehrpwm", "tbclk", "ehrpwm0_tbclk"),
- DT_CLK("48302200.ehrpwm", "tbclk", "ehrpwm1_tbclk"),
- DT_CLK("48304200.ehrpwm", "tbclk", "ehrpwm2_tbclk"),
- DT_CLK("48306200.ehrpwm", "tbclk", "ehrpwm3_tbclk"),
- DT_CLK("48308200.ehrpwm", "tbclk", "ehrpwm4_tbclk"),
- DT_CLK("4830a200.ehrpwm", "tbclk", "ehrpwm5_tbclk"),
- DT_CLK("48300200.pwm", "tbclk", "ehrpwm0_tbclk"),
- DT_CLK("48302200.pwm", "tbclk", "ehrpwm1_tbclk"),
- DT_CLK("48304200.pwm", "tbclk", "ehrpwm2_tbclk"),
- DT_CLK("48306200.pwm", "tbclk", "ehrpwm3_tbclk"),
- DT_CLK("48308200.pwm", "tbclk", "ehrpwm4_tbclk"),
- DT_CLK("4830a200.pwm", "tbclk", "ehrpwm5_tbclk"),
+ DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0348:8"),
+ DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0458:8"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0460:8"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0468:8"),
+ DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0470:8"),
+ DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0478:8"),
+ DT_CLK(NULL, "synctimer_32kclk", "l4_wkup_cm:0210:8"),
+ DT_CLK(NULL, "usb_otg_ss0_refclk960m", "l4_per_cm:0240:8"),
+ DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l4_per_cm:0248:8"),
{ .node_name = NULL },
};
@@ -133,6 +232,8 @@ int __init am43xx_dt_clk_init(void)
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
+
/*
* cpsw_cpts_rft_clk has got the choice of 3 clocksources
* dpll_core_m4_ck, dpll_core_m5_ck and dpll_disp_m2_ck.
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 2005f03..339d30d 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -35,7 +35,7 @@
#define OMAP4_DPLL_USB_DEFFREQ 960000000
static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
- { OMAP4_MPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_mpu_m2_ck" },
+ { OMAP4_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
{ 0 },
};
@@ -59,7 +59,7 @@ static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
};
static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
- "dmic_sync_mux_ck",
+ "abe_cm:clk:0018:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -79,7 +79,7 @@ static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
};
static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
- "mcasp_sync_mux_ck",
+ "abe_cm:clk:0020:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -92,7 +92,7 @@ static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
};
static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
- "mcbsp1_sync_mux_ck",
+ "abe_cm:clk:0028:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -105,7 +105,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst =
};
static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
- "mcbsp2_sync_mux_ck",
+ "abe_cm:clk:0030:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -118,7 +118,7 @@ static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst =
};
static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
- "mcbsp3_sync_mux_ck",
+ "abe_cm:clk:0038:26",
"pad_clks_ck",
"slimbus_clk",
NULL,
@@ -186,18 +186,18 @@ static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst =
static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
- { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "aess_fclk" },
+ { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
- { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "func_dmic_abe_gfclk" },
- { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "func_mcasp_abe_gfclk" },
- { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "func_mcbsp1_gfclk" },
- { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "func_mcbsp2_gfclk" },
- { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "func_mcbsp3_gfclk" },
- { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "slimbus1_fclk_0" },
- { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "timer5_sync_mux" },
- { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "timer6_sync_mux" },
- { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "timer7_sync_mux" },
- { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "timer8_sync_mux" },
+ { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
+ { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
+ { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
+ { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
+ { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
+ { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
+ { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
+ { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
+ { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
+ { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
};
@@ -280,6 +280,7 @@ static const char * const omap4_fdif_fck_parents[] __initconst = {
static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
.max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
@@ -289,7 +290,7 @@ static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
- { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "fdif_fck" },
+ { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
{ 0 },
};
@@ -322,7 +323,7 @@ static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst
};
static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
- { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "dss_dss_clk" },
+ { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
{ 0 },
};
@@ -338,7 +339,7 @@ static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
};
static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
- { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "sgx_clk_mux" },
+ { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
{ 0 },
};
@@ -365,6 +366,7 @@ static const char * const omap4_hsi_fck_parents[] __initconst = {
static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
.max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
@@ -373,12 +375,12 @@ static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
};
static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
- "utmi_p1_gfclk",
+ "l3_init_cm:clk:0038:24",
NULL,
};
static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
- "utmi_p2_gfclk",
+ "l3_init_cm:clk:0038:25",
NULL,
};
@@ -419,7 +421,7 @@ static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initcon
};
static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
- "otg_60m_gfclk",
+ "l3_init_cm:clk:0040:24",
NULL,
};
@@ -453,14 +455,14 @@ static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __ini
};
static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
- { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "hsmmc1_fclk" },
- { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "hsmmc2_fclk" },
- { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "hsi_fck" },
+ { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
+ { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
+ { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
- { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "ocp2scp_usb_phy_phy_48m" },
+ { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
{ 0 },
};
@@ -531,7 +533,7 @@ static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
};
static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
- "mcbsp4_sync_mux_ck",
+ "l4_per_cm:clk:00c0:26",
"pad_clks_ck",
NULL,
};
@@ -544,7 +546,7 @@ static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
{ 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
- { 25, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
+ { 26, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
{ 0 },
};
@@ -571,12 +573,12 @@ static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst
};
static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
- { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "cm2_dm10_mux" },
- { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "cm2_dm11_mux" },
- { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "cm2_dm2_mux" },
- { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "cm2_dm3_mux" },
- { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "cm2_dm4_mux" },
- { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "cm2_dm9_mux" },
+ { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
+ { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
+ { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
+ { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
+ { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
+ { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
@@ -589,14 +591,14 @@ static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initcons
{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
- { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "per_mcbsp4_gfclk" },
+ { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
- { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "slimbus2_fclk_0" },
+ { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
@@ -619,7 +621,7 @@ static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initcon
{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
- { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "dmt1_clk_mux" },
+ { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
{ 0 },
@@ -633,7 +635,7 @@ static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
};
static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
- "pmd_trace_clk_mux_ck",
+ "emu_sys_cm:clk:0000:22",
NULL,
};
@@ -651,12 +653,13 @@ static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __init
};
static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
- "pmd_stm_clock_mux_ck",
+ "emu_sys_cm:clk:0000:20",
NULL,
};
static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
.max_div = 64,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
};
static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
@@ -697,52 +700,79 @@ const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
};
static struct ti_dt_clk omap44xx_clks[] = {
- DT_CLK("smp_twd", NULL, "mpu_periphclk"),
- DT_CLK("omapdss_dss", "ick", "dss_fck"),
- DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
- DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
- DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
- DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
- DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
- DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "uart1_ick", "dummy_ck"),
- DT_CLK(NULL, "uart2_ick", "dummy_ck"),
- DT_CLK(NULL, "uart3_ick", "dummy_ck"),
- DT_CLK(NULL, "uart4_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
- DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
- DT_CLK("omap_wdt", "ick", "dummy_ck"),
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
- DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"),
- DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"),
- DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
- DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
- DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
+ /*
+ * XXX: All the clock aliases below are only needed for legacy
+ * hwmod support. Once hwmod is removed, these can be removed
+ * also.
+ */
+ DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
+ DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
+ DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
+ DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
+ DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
+ DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
+ DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
+ DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
+ DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
+ DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
+ DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
+ DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
+ DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
+ DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
+ DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
+ DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
+ DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
+ DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
+ DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
+ DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
+ DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
+ DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
+ DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
+ DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
+ DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
+ DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
+ DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
+ DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
+ DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
+ DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
+ DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
+ DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
+ DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
+ DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
+ DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
+ DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
+ DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
+ DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
+ DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
+ DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
+ DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
+ DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
+ DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
+ DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
+ DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
+ DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
+ DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
+ DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
+ DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
{ .node_name = NULL },
};
diff --git a/drivers/clk/ti/clk-54xx.c b/drivers/clk/ti/clk-54xx.c
index 294bc03..a17b0c4 100644
--- a/drivers/clk/ti/clk-54xx.c
+++ b/drivers/clk/ti/clk-54xx.c
@@ -16,6 +16,7 @@
#include <linux/clkdev.h>
#include <linux/io.h>
#include <linux/clk/ti.h>
+#include <dt-bindings/clock/omap5.h>
#include "clock.h"
@@ -27,201 +28,511 @@
*/
#define OMAP5_DPLL_USB_DEFFREQ 960000000
+static const struct omap_clkctrl_reg_data omap5_mpu_clkctrl_regs[] __initconst = {
+ { OMAP5_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_dsp_clkctrl_regs[] __initconst = {
+ { OMAP5_MMU_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_h11x2_ck" },
+ { 0 },
+};
+
+static const char * const omap5_dmic_gfclk_parents[] __initconst = {
+ "abe_cm:clk:0018:26",
+ "pad_clks_ck",
+ "slimbus_clk",
+ NULL,
+};
+
+static const char * const omap5_dmic_sync_mux_ck_parents[] __initconst = {
+ "abe_24m_fclk",
+ "dss_syc_gfclk_div",
+ "func_24m_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_dmic_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_dmic_gfclk_parents, NULL },
+ { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
+ "abe_cm:clk:0028:26",
+ "pad_clks_ck",
+ "slimbus_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_mcbsp1_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_mcbsp1_gfclk_parents, NULL },
+ { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
+ "abe_cm:clk:0030:26",
+ "pad_clks_ck",
+ "slimbus_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_mcbsp2_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_mcbsp2_gfclk_parents, NULL },
+ { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
+ "abe_cm:clk:0038:26",
+ "pad_clks_ck",
+ "slimbus_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_mcbsp3_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_mcbsp3_gfclk_parents, NULL },
+ { 26, TI_CLK_MUX, omap5_dmic_sync_mux_ck_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_timer5_gfclk_mux_parents[] __initconst = {
+ "dss_syc_gfclk_div",
+ "sys_32k_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer5_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer6_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer7_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer8_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
+ { OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
+ { OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
+ { OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
+ { OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
+ { OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
+ { OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
+ { OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
+ { OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
+ { OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
+ { OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l3main1_clkctrl_regs[] __initconst = {
+ { OMAP5_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l3main2_clkctrl_regs[] __initconst = {
+ { OMAP5_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_ipu_clkctrl_regs[] __initconst = {
+ { OMAP5_MMU_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h22x2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_dma_clkctrl_regs[] __initconst = {
+ { OMAP5_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_emif_clkctrl_regs[] __initconst = {
+ { OMAP5_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { OMAP5_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
+ { OMAP5_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h11x2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l4cfg_clkctrl_regs[] __initconst = {
+ { OMAP5_L4_CFG_CLKCTRL, NULL, 0, "l4_root_clk_div" },
+ { OMAP5_SPINLOCK_CLKCTRL, NULL, 0, "l4_root_clk_div" },
+ { OMAP5_MAILBOX_CLKCTRL, NULL, 0, "l4_root_clk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l3instr_clkctrl_regs[] __initconst = {
+ { OMAP5_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { OMAP5_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { 0 },
+};
+
+static const char * const omap5_timer10_gfclk_mux_parents[] __initconst = {
+ "sys_clkin",
+ "sys_32k_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer10_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer11_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer2_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer3_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer4_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer9_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_gpio2_dbclk_parents[] __initconst = {
+ "sys_32k_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio3_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio4_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio5_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio6_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio7_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio8_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
+ { OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
+ { OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
+ { OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
+ { OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
+ { OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
+ { OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
+ { OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_GPIO5_CLKCTRL, omap5_gpio5_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_GPIO6_CLKCTRL, omap5_gpio6_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_L4_PER_CLKCTRL, NULL, 0, "l4_root_clk_div" },
+ { OMAP5_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_GPIO7_CLKCTRL, omap5_gpio7_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_GPIO8_CLKCTRL, omap5_gpio8_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { OMAP5_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { 0 },
+};
+
+static const char * const omap5_dss_dss_clk_parents[] __initconst = {
+ "dpll_per_h12x2_ck",
+ NULL,
+};
+
+static const char * const omap5_dss_48mhz_clk_parents[] __initconst = {
+ "func_48m_fclk",
+ NULL,
+};
+
+static const char * const omap5_dss_sys_clk_parents[] __initconst = {
+ "dss_syc_gfclk_div",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_dss_core_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_dss_dss_clk_parents, NULL },
+ { 9, TI_CLK_GATE, omap5_dss_48mhz_clk_parents, NULL },
+ { 10, TI_CLK_GATE, omap5_dss_sys_clk_parents, NULL },
+ { 11, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
+ { OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
+ { 0 },
+};
+
+static const char * const omap5_mmc1_fclk_mux_parents[] __initconst = {
+ "func_128m_clk",
+ "dpll_per_m2x2_ck",
+ NULL,
+};
+
+static const char * const omap5_mmc1_fclk_parents[] __initconst = {
+ "l3init_cm:clk:0008:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data omap5_mmc1_fclk_data __initconst = {
+ .max_div = 2,
+};
+
+static const struct omap_clkctrl_bit_data omap5_mmc1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, omap5_mmc1_fclk_parents, &omap5_mmc1_fclk_data },
+ { 0 },
+};
+
+static const char * const omap5_mmc2_fclk_parents[] __initconst = {
+ "l3init_cm:clk:0010:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data omap5_mmc2_fclk_data __initconst = {
+ .max_div = 2,
+};
+
+static const struct omap_clkctrl_bit_data omap5_mmc2_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_mmc1_fclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, omap5_mmc2_fclk_parents, &omap5_mmc2_fclk_data },
+ { 0 },
+};
+
+static const char * const omap5_usb_host_hs_hsic60m_p3_clk_parents[] __initconst = {
+ "l3init_60m_fclk",
+ NULL,
+};
+
+static const char * const omap5_usb_host_hs_hsic480m_p3_clk_parents[] __initconst = {
+ "dpll_usb_m2_ck",
+ NULL,
+};
+
+static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
+ "l3init_cm:clk:0038:24",
+ NULL,
+};
+
+static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
+ "l3init_cm:clk:0038:25",
+ NULL,
+};
+
+static const char * const omap5_utmi_p1_gfclk_parents[] __initconst = {
+ "l3init_60m_fclk",
+ "xclk60mhsp1_ck",
+ NULL,
+};
+
+static const char * const omap5_utmi_p2_gfclk_parents[] __initconst = {
+ "l3init_60m_fclk",
+ "xclk60mhsp2_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_usb_host_hs_bit_data[] __initconst = {
+ { 6, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 7, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
+ { 8, TI_CLK_GATE, omap5_usb_host_hs_utmi_p1_clk_parents, NULL },
+ { 9, TI_CLK_GATE, omap5_usb_host_hs_utmi_p2_clk_parents, NULL },
+ { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 11, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 12, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 13, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
+ { 14, TI_CLK_GATE, omap5_usb_host_hs_hsic480m_p3_clk_parents, NULL },
+ { 24, TI_CLK_MUX, omap5_utmi_p1_gfclk_parents, NULL },
+ { 25, TI_CLK_MUX, omap5_utmi_p2_gfclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_usb_tll_hs_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 9, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 10, TI_CLK_GATE, omap5_usb_host_hs_hsic60m_p3_clk_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_sata_ref_clk_parents[] __initconst = {
+ "sys_clkin",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_sata_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_sata_ref_clk_parents, NULL },
+ { 0 },
+};
+
+static const char * const omap5_usb_otg_ss_refclk960m_parents[] __initconst = {
+ "dpll_usb_clkdcoldo",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data omap5_usb_otg_ss_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_usb_otg_ss_refclk960m_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
+ { OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
+ { OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
+ { OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
+ { OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
+ { OMAP5_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
+ { OMAP5_USB_OTG_SS_CLKCTRL, omap5_usb_otg_ss_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_gpio1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, omap5_gpio2_dbclk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data omap5_timer1_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, omap5_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data omap5_wkupaon_clkctrl_regs[] __initconst = {
+ { OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
+ { OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+ { OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
+ { OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
+ { OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
+ { OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data omap5_clkctrl_data[] __initconst = {
+ { 0x4a004320, omap5_mpu_clkctrl_regs },
+ { 0x4a004420, omap5_dsp_clkctrl_regs },
+ { 0x4a004520, omap5_abe_clkctrl_regs },
+ { 0x4a008720, omap5_l3main1_clkctrl_regs },
+ { 0x4a008820, omap5_l3main2_clkctrl_regs },
+ { 0x4a008920, omap5_ipu_clkctrl_regs },
+ { 0x4a008a20, omap5_dma_clkctrl_regs },
+ { 0x4a008b20, omap5_emif_clkctrl_regs },
+ { 0x4a008d20, omap5_l4cfg_clkctrl_regs },
+ { 0x4a008e20, omap5_l3instr_clkctrl_regs },
+ { 0x4a009020, omap5_l4per_clkctrl_regs },
+ { 0x4a009420, omap5_dss_clkctrl_regs },
+ { 0x4a009620, omap5_l3init_clkctrl_regs },
+ { 0x4ae07920, omap5_wkupaon_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk omap54xx_clks[] = {
- DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
- DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
- DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
- DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
- DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
- DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
- DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
- DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
- DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
- DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
- DT_CLK(NULL, "sys_clkin", "sys_clkin"),
- DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
- DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
- DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
- DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
- DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
- DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
- DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
- DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
- DT_CLK(NULL, "abe_clk", "abe_clk"),
- DT_CLK(NULL, "abe_iclk", "abe_iclk"),
- DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
- DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_h21x2_ck", "dpll_core_h21x2_ck"),
- DT_CLK(NULL, "c2c_fclk", "c2c_fclk"),
- DT_CLK(NULL, "c2c_iclk", "c2c_iclk"),
- DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
- DT_CLK(NULL, "dpll_core_h11x2_ck", "dpll_core_h11x2_ck"),
- DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
- DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
- DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
- DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
- DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
- DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
- DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
- DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
- DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
- DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
- DT_CLK(NULL, "dpll_iva_h11x2_ck", "dpll_iva_h11x2_ck"),
- DT_CLK(NULL, "dpll_iva_h12x2_ck", "dpll_iva_h12x2_ck"),
- DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
- DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
- DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
- DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
- DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
- DT_CLK(NULL, "dpll_unipro1_ck", "dpll_unipro1_ck"),
- DT_CLK(NULL, "dpll_unipro1_clkdcoldo", "dpll_unipro1_clkdcoldo"),
- DT_CLK(NULL, "dpll_unipro1_m2_ck", "dpll_unipro1_m2_ck"),
- DT_CLK(NULL, "dpll_unipro2_ck", "dpll_unipro2_ck"),
- DT_CLK(NULL, "dpll_unipro2_clkdcoldo", "dpll_unipro2_clkdcoldo"),
- DT_CLK(NULL, "dpll_unipro2_m2_ck", "dpll_unipro2_m2_ck"),
- DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
- DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
- DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
- DT_CLK(NULL, "dss_syc_gfclk_div", "dss_syc_gfclk_div"),
- DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
- DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
- DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
- DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
- DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
- DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
- DT_CLK(NULL, "gpu_l3_iclk", "gpu_l3_iclk"),
- DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
- DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
- DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
- DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
- DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
- DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
- DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
- DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
- DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
- DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
- DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
- DT_CLK(NULL, "lli_txphy_clk", "lli_txphy_clk"),
- DT_CLK(NULL, "lli_txphy_ls_clk", "lli_txphy_ls_clk"),
- DT_CLK(NULL, "mmc1_32khz_clk", "mmc1_32khz_clk"),
- DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
- DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "usb_host_hs_hsic480m_p3_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "usb_host_hs_hsic60m_p3_clk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
- DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
- DT_CLK(NULL, "usb_otg_ss_refclk960m", "usb_otg_ss_refclk960m"),
- DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
- DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
- DT_CLK(NULL, "aess_fclk", "aess_fclk"),
- DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
- DT_CLK(NULL, "dmic_gfclk", "dmic_gfclk"),
- DT_CLK(NULL, "fdif_fclk", "fdif_fclk"),
- DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
- DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
- DT_CLK(NULL, "hsi_fclk", "hsi_fclk"),
- DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
- DT_CLK(NULL, "mcasp_gfclk", "mcasp_gfclk"),
- DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
- DT_CLK(NULL, "mcbsp1_gfclk", "mcbsp1_gfclk"),
- DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
- DT_CLK(NULL, "mcbsp2_gfclk", "mcbsp2_gfclk"),
- DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
- DT_CLK(NULL, "mcbsp3_gfclk", "mcbsp3_gfclk"),
- DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
- DT_CLK(NULL, "mmc1_fclk", "mmc1_fclk"),
- DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
- DT_CLK(NULL, "mmc2_fclk", "mmc2_fclk"),
- DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
- DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
- DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
- DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
- DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
- DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
- DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
- DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
- DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
- DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
- DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
- DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
- DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
- DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
- DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
- DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
- DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
- DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
- DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
- DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
- DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
- DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
- DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
- DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
- DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
- DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "uart1_ick", "dummy_ck"),
- DT_CLK(NULL, "uart2_ick", "dummy_ck"),
- DT_CLK(NULL, "uart3_ick", "dummy_ck"),
- DT_CLK(NULL, "uart4_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
- DT_CLK("omap_wdt", "ick", "dummy_ck"),
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
- DT_CLK("4ae18000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin"),
- DT_CLK("40138000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
- DT_CLK("4013a000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
- DT_CLK("4013c000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
- DT_CLK("4013e000.timer", "timer_sys_ck", "dss_syc_gfclk_div"),
+ DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
+ DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
+ DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
+ DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
+ DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
+ DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
+ DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
+ DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
+ DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
+ DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
+ DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
+ DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
+ DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
+ DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
+ DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
+ DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
+ DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
+ DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
+ DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
+ DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
+ DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
+ DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
+ DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
+ DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
+ DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
+ DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
{ .node_name = NULL },
};
@@ -234,6 +545,8 @@ int __init omap5xxx_dt_clk_init(void)
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
+
abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_clk_mux");
sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 9fd6043..fb249a1 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -15,297 +15,809 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk/ti.h>
+#include <dt-bindings/clock/dra7.h>
#include "clock.h"
#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
#define DRA7_DPLL_USB_DEFFREQ 960000000
+static const struct omap_clkctrl_reg_data dra7_mpu_clkctrl_regs[] __initconst = {
+ { DRA7_MPU_CLKCTRL, NULL, 0, "dpll_mpu_m2_ck" },
+ { 0 },
+};
+
+static const char * const dra7_mcasp1_aux_gfclk_mux_parents[] __initconst = {
+ "per_abe_x1_gfclk2_div",
+ "video1_clk2_div",
+ "video2_clk2_div",
+ "hdmi_clk2_div",
+ NULL,
+};
+
+static const char * const dra7_mcasp1_ahclkx_mux_parents[] __initconst = {
+ "abe_24m_fclk",
+ "abe_sys_clk_div",
+ "func_24m_clk",
+ "atl_clkin3_ck",
+ "atl_clkin2_ck",
+ "atl_clkin1_ck",
+ "atl_clkin0_ck",
+ "sys_clkin2",
+ "ref_clkin0_ck",
+ "ref_clkin1_ck",
+ "ref_clkin2_ck",
+ "ref_clkin3_ck",
+ "mlb_clk",
+ "mlbp_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp1_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_timer5_gfclk_mux_parents[] __initconst = {
+ "timer_sys_clk_div",
+ "sys_32k_ck",
+ "sys_clkin2",
+ "ref_clkin0_ck",
+ "ref_clkin1_ck",
+ "ref_clkin2_ck",
+ "ref_clkin3_ck",
+ "abe_giclk_div",
+ "video1_div_clk",
+ "video2_div_clk",
+ "hdmi_div_clk",
+ "clkoutmux0_clk_mux",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer5_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer6_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer7_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer8_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer5_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_uart6_gfclk_mux_parents[] __initconst = {
+ "func_48m_fclk",
+ "dpll_per_m2x2_ck",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart6_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_ipu_clkctrl_regs[] __initconst = {
+ { DRA7_MCASP1_CLKCTRL, dra7_mcasp1_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0010:22" },
+ { DRA7_TIMER5_CLKCTRL, dra7_timer5_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0018:24" },
+ { DRA7_TIMER6_CLKCTRL, dra7_timer6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0020:24" },
+ { DRA7_TIMER7_CLKCTRL, dra7_timer7_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0028:24" },
+ { DRA7_TIMER8_CLKCTRL, dra7_timer8_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0030:24" },
+ { DRA7_I2C5_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { DRA7_UART6_CLKCTRL, dra7_uart6_bit_data, CLKF_SW_SUP, "ipu_cm:clk:0040:24" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_rtc_clkctrl_regs[] __initconst = {
+ { DRA7_RTCSS_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_coreaon_clkctrl_regs[] __initconst = {
+ { DRA7_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
+ { DRA7_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "wkupaon_iclk_mux" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_l3main1_clkctrl_regs[] __initconst = {
+ { DRA7_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_TPCC_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_TPTC0_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_TPTC1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_VCP1_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_VCP2_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_dma_clkctrl_regs[] __initconst = {
+ { DRA7_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_emif_clkctrl_regs[] __initconst = {
+ { DRA7_DMM_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const char * const dra7_atl_dpll_clk_mux_parents[] __initconst = {
+ "sys_32k_ck",
+ "video1_clkin_ck",
+ "video2_clkin_ck",
+ "hdmi_clkin_ck",
+ NULL,
+};
+
+static const char * const dra7_atl_gfclk_mux_parents[] __initconst = {
+ "l3_iclk_div",
+ "dpll_abe_m2_ck",
+ "atl_cm:clk:0000:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_atl_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_atl_dpll_clk_mux_parents, NULL },
+ { 26, TI_CLK_MUX, dra7_atl_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_atl_clkctrl_regs[] __initconst = {
+ { DRA7_ATL_CLKCTRL, dra7_atl_bit_data, CLKF_SW_SUP, "atl_cm:clk:0000:26" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_l4cfg_clkctrl_regs[] __initconst = {
+ { DRA7_L4_CFG_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_SPINLOCK_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX1_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX2_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX3_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX4_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX5_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX6_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX7_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX8_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX9_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX10_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX11_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX12_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_MAILBOX13_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_l3instr_clkctrl_regs[] __initconst = {
+ { DRA7_L3_MAIN_2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },
+ { 0 },
+};
+
+static const char * const dra7_dss_dss_clk_parents[] __initconst = {
+ "dpll_per_h12x2_ck",
+ NULL,
+};
+
+static const char * const dra7_dss_48mhz_clk_parents[] __initconst = {
+ "func_48m_fclk",
+ NULL,
+};
+
+static const char * const dra7_dss_hdmi_clk_parents[] __initconst = {
+ "hdmi_dpll_clk_mux",
+ NULL,
+};
+
+static const char * const dra7_dss_32khz_clk_parents[] __initconst = {
+ "sys_32k_ck",
+ NULL,
+};
+
+static const char * const dra7_dss_video1_clk_parents[] __initconst = {
+ "video1_dpll_clk_mux",
+ NULL,
+};
+
+static const char * const dra7_dss_video2_clk_parents[] __initconst = {
+ "video2_dpll_clk_mux",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_dss_core_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_dss_clk_parents, NULL },
+ { 9, TI_CLK_GATE, dra7_dss_48mhz_clk_parents, NULL },
+ { 10, TI_CLK_GATE, dra7_dss_hdmi_clk_parents, NULL },
+ { 11, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 12, TI_CLK_GATE, dra7_dss_video1_clk_parents, NULL },
+ { 13, TI_CLK_GATE, dra7_dss_video2_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_dss_clkctrl_regs[] __initconst = {
+ { DRA7_DSS_CORE_CLKCTRL, dra7_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
+ { DRA7_BB2D_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_h24x2_ck" },
+ { 0 },
+};
+
+static const char * const dra7_mmc1_fclk_mux_parents[] __initconst = {
+ "func_128m_clk",
+ "dpll_per_m2x2_ck",
+ NULL,
+};
+
+static const char * const dra7_mmc1_fclk_div_parents[] __initconst = {
+ "l3init_cm:clk:0008:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data dra7_mmc1_fclk_div_data __initconst = {
+ .max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const struct omap_clkctrl_bit_data dra7_mmc1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, dra7_mmc1_fclk_div_parents, &dra7_mmc1_fclk_div_data },
+ { 0 },
+};
+
+static const char * const dra7_mmc2_fclk_div_parents[] __initconst = {
+ "l3init_cm:clk:0010:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data dra7_mmc2_fclk_div_data __initconst = {
+ .max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const struct omap_clkctrl_bit_data dra7_mmc2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mmc1_fclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, dra7_mmc2_fclk_div_parents, &dra7_mmc2_fclk_div_data },
+ { 0 },
+};
+
+static const char * const dra7_usb_otg_ss2_refclk960m_parents[] __initconst = {
+ "l3init_960m_gfclk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_usb_otg_ss2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_sata_ref_clk_parents[] __initconst = {
+ "sys_clkin1",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_sata_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_sata_ref_clk_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_optfclk_pciephy1_clk_parents[] __initconst = {
+ "apll_pcie_ck",
+ NULL,
+};
+
+static const char * const dra7_optfclk_pciephy1_div_clk_parents[] __initconst = {
+ "optfclk_pciephy_div",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_pcie1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
+ { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_pcie2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 9, TI_CLK_GATE, dra7_optfclk_pciephy1_clk_parents, NULL },
+ { 10, TI_CLK_GATE, dra7_optfclk_pciephy1_div_clk_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_rmii_50mhz_clk_mux_parents[] __initconst = {
+ "dpll_gmac_h11x2_ck",
+ "rmii_clk_ck",
+ NULL,
+};
+
+static const char * const dra7_gmac_rft_clk_mux_parents[] __initconst = {
+ "video1_clkin_ck",
+ "video2_clkin_ck",
+ "dpll_abe_m2_ck",
+ "hdmi_clkin_ck",
+ "l3_iclk_div",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_rmii_50mhz_clk_mux_parents, NULL },
+ { 25, TI_CLK_MUX, dra7_gmac_rft_clk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_usb_otg_ss1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_usb_otg_ss2_refclk960m_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_l3init_clkctrl_regs[] __initconst = {
+ { DRA7_MMC1_CLKCTRL, dra7_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
+ { DRA7_MMC2_CLKCTRL, dra7_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
+ { DRA7_USB_OTG_SS2_CLKCTRL, dra7_usb_otg_ss2_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+ { DRA7_USB_OTG_SS3_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+ { DRA7_USB_OTG_SS4_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+ { DRA7_SATA_CLKCTRL, dra7_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
+ { DRA7_PCIE1_CLKCTRL, dra7_pcie1_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
+ { DRA7_PCIE2_CLKCTRL, dra7_pcie2_bit_data, CLKF_SW_SUP, "l4_root_clk_div", "pcie_clkdm" },
+ { DRA7_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck", "gmac_clkdm" },
+ { DRA7_OCP2SCP1_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
+ { DRA7_OCP2SCP3_CLKCTRL, NULL, CLKF_HW_SUP, "l4_root_clk_div" },
+ { DRA7_USB_OTG_SS1_CLKCTRL, dra7_usb_otg_ss1_bit_data, CLKF_HW_SUP, "dpll_core_h13x2_ck" },
+ { 0 },
+};
+
+static const char * const dra7_timer10_gfclk_mux_parents[] __initconst = {
+ "timer_sys_clk_div",
+ "sys_32k_ck",
+ "sys_clkin2",
+ "ref_clkin0_ck",
+ "ref_clkin1_ck",
+ "ref_clkin2_ck",
+ "ref_clkin3_ck",
+ "abe_giclk_div",
+ "video1_div_clk",
+ "video2_div_clk",
+ "hdmi_div_clk",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer10_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer11_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer2_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer3_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer4_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer9_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio2_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio3_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio4_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio5_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio6_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer13_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer14_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer15_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio7_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio8_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_mmc3_gfclk_div_parents[] __initconst = {
+ "l4per_cm:clk:0120:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data dra7_mmc3_gfclk_div_data __initconst = {
+ .max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const struct omap_clkctrl_bit_data dra7_mmc3_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, dra7_mmc3_gfclk_div_parents, &dra7_mmc3_gfclk_div_data },
+ { 0 },
+};
+
+static const char * const dra7_mmc4_gfclk_div_parents[] __initconst = {
+ "l4per_cm:clk:0128:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data dra7_mmc4_gfclk_div_data __initconst = {
+ .max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const struct omap_clkctrl_bit_data dra7_mmc4_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, dra7_mmc4_gfclk_div_parents, &dra7_mmc4_gfclk_div_data },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer16_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_qspi_gfclk_mux_parents[] __initconst = {
+ "func_128m_clk",
+ "dpll_per_h13x2_ck",
+ NULL,
+};
+
+static const char * const dra7_qspi_gfclk_div_parents[] __initconst = {
+ "l4per_cm:clk:0138:24",
+ NULL,
+};
+
+static const struct omap_clkctrl_div_data dra7_qspi_gfclk_div_data __initconst = {
+ .max_div = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+};
+
+static const struct omap_clkctrl_bit_data dra7_qspi_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_qspi_gfclk_mux_parents, NULL },
+ { 25, TI_CLK_DIVIDER, dra7_qspi_gfclk_div_parents, &dra7_qspi_gfclk_div_data },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart1_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart2_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart3_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart4_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp2_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 28, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp3_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart5_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp5_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp8_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp4_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart7_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart8_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart9_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp6_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_mcasp7_bit_data[] __initconst = {
+ { 22, TI_CLK_MUX, dra7_mcasp1_aux_gfclk_mux_parents, NULL },
+ { 24, TI_CLK_MUX, dra7_mcasp1_ahclkx_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst = {
+ { DRA7_L4_PER2_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per2_clkdm" },
+ { DRA7_L4_PER3_CLKCTRL, NULL, 0, "l3_iclk_div", "l4per3_clkdm" },
+ { DRA7_TIMER10_CLKCTRL, dra7_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
+ { DRA7_TIMER11_CLKCTRL, dra7_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
+ { DRA7_TIMER2_CLKCTRL, dra7_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0038:24" },
+ { DRA7_TIMER3_CLKCTRL, dra7_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0040:24" },
+ { DRA7_TIMER4_CLKCTRL, dra7_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0048:24" },
+ { DRA7_TIMER9_CLKCTRL, dra7_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0050:24" },
+ { DRA7_ELM_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_GPIO2_CLKCTRL, dra7_gpio2_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_GPIO3_CLKCTRL, dra7_gpio3_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_GPIO4_CLKCTRL, dra7_gpio4_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_GPIO5_CLKCTRL, dra7_gpio5_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_GPIO6_CLKCTRL, dra7_gpio6_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
+ { DRA7_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
+ { DRA7_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
+ { DRA7_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { DRA7_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { DRA7_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { DRA7_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
+ { DRA7_L4_PER1_CLKCTRL, NULL, 0, "l3_iclk_div" },
+ { DRA7_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4_root_clk_div", "l4per2_clkdm" },
+ { DRA7_TIMER13_CLKCTRL, dra7_timer13_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00c8:24", "l4per3_clkdm" },
+ { DRA7_TIMER14_CLKCTRL, dra7_timer14_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d0:24", "l4per3_clkdm" },
+ { DRA7_TIMER15_CLKCTRL, dra7_timer15_bit_data, CLKF_SW_SUP, "l4per_cm:clk:00d8:24", "l4per3_clkdm" },
+ { DRA7_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { DRA7_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { DRA7_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { DRA7_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
+ { DRA7_GPIO7_CLKCTRL, dra7_gpio7_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_GPIO8_CLKCTRL, dra7_gpio8_bit_data, CLKF_HW_SUP, "l3_iclk_div" },
+ { DRA7_MMC3_CLKCTRL, dra7_mmc3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0120:25" },
+ { DRA7_MMC4_CLKCTRL, dra7_mmc4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0128:25" },
+ { DRA7_TIMER16_CLKCTRL, dra7_timer16_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0130:24", "l4per3_clkdm" },
+ { DRA7_QSPI_CLKCTRL, dra7_qspi_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0138:25", "l4per2_clkdm" },
+ { DRA7_UART1_CLKCTRL, dra7_uart1_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0140:24" },
+ { DRA7_UART2_CLKCTRL, dra7_uart2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0148:24" },
+ { DRA7_UART3_CLKCTRL, dra7_uart3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0150:24" },
+ { DRA7_UART4_CLKCTRL, dra7_uart4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0158:24" },
+ { DRA7_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0160:22", "l4per2_clkdm" },
+ { DRA7_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0168:22", "l4per2_clkdm" },
+ { DRA7_UART5_CLKCTRL, dra7_uart5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0170:24" },
+ { DRA7_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0178:22", "l4per2_clkdm" },
+ { DRA7_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0190:24", "l4per2_clkdm" },
+ { DRA7_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0198:22", "l4per2_clkdm" },
+ { DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+ { DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+ { DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+ { DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+ { DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },
+ { DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },
+ { DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
+ { DRA7_UART9_CLKCTRL, dra7_uart9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e8:24", "l4per2_clkdm" },
+ { DRA7_DCAN2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin1", "l4per2_clkdm" },
+ { DRA7_MCASP6_CLKCTRL, dra7_mcasp6_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0204:22", "l4per2_clkdm" },
+ { DRA7_MCASP7_CLKCTRL, dra7_mcasp7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0208:22", "l4per2_clkdm" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_gpio1_bit_data[] __initconst = {
+ { 8, TI_CLK_GATE, dra7_dss_32khz_clk_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_timer1_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_timer10_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_bit_data dra7_uart10_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_uart6_gfclk_mux_parents, NULL },
+ { 0 },
+};
+
+static const char * const dra7_dcan1_sys_clk_mux_parents[] __initconst = {
+ "sys_clkin1",
+ "sys_clkin2",
+ NULL,
+};
+
+static const struct omap_clkctrl_bit_data dra7_dcan1_bit_data[] __initconst = {
+ { 24, TI_CLK_MUX, dra7_dcan1_sys_clk_mux_parents, NULL },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initconst = {
+ { DRA7_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
+ { DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
+ { DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
+ { DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
+ { DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },
+ { DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
+ { DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
+ { DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data dra7_clkctrl_data[] __initconst = {
+ { 0x4a005320, dra7_mpu_clkctrl_regs },
+ { 0x4a005540, dra7_ipu_clkctrl_regs },
+ { 0x4a005740, dra7_rtc_clkctrl_regs },
+ { 0x4a008620, dra7_coreaon_clkctrl_regs },
+ { 0x4a008720, dra7_l3main1_clkctrl_regs },
+ { 0x4a008a20, dra7_dma_clkctrl_regs },
+ { 0x4a008b20, dra7_emif_clkctrl_regs },
+ { 0x4a008c00, dra7_atl_clkctrl_regs },
+ { 0x4a008d20, dra7_l4cfg_clkctrl_regs },
+ { 0x4a008e20, dra7_l3instr_clkctrl_regs },
+ { 0x4a009120, dra7_dss_clkctrl_regs },
+ { 0x4a009320, dra7_l3init_clkctrl_regs },
+ { 0x4a009700, dra7_l4per_clkctrl_regs },
+ { 0x4ae07820, dra7_wkupaon_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk dra7xx_clks[] = {
- DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
- DT_CLK(NULL, "atl_clkin1_ck", "atl_clkin1_ck"),
- DT_CLK(NULL, "atl_clkin2_ck", "atl_clkin2_ck"),
- DT_CLK(NULL, "atl_clkin3_ck", "atl_clkin3_ck"),
- DT_CLK(NULL, "hdmi_clkin_ck", "hdmi_clkin_ck"),
- DT_CLK(NULL, "mlb_clkin_ck", "mlb_clkin_ck"),
- DT_CLK(NULL, "mlbp_clkin_ck", "mlbp_clkin_ck"),
- DT_CLK(NULL, "pciesref_acs_clk_ck", "pciesref_acs_clk_ck"),
- DT_CLK(NULL, "ref_clkin0_ck", "ref_clkin0_ck"),
- DT_CLK(NULL, "ref_clkin1_ck", "ref_clkin1_ck"),
- DT_CLK(NULL, "ref_clkin2_ck", "ref_clkin2_ck"),
- DT_CLK(NULL, "ref_clkin3_ck", "ref_clkin3_ck"),
- DT_CLK(NULL, "rmii_clk_ck", "rmii_clk_ck"),
- DT_CLK(NULL, "sdvenc_clkin_ck", "sdvenc_clkin_ck"),
- DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
- DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
- DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
- DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
- DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
- DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
- DT_CLK(NULL, "virt_20000000_ck", "virt_20000000_ck"),
- DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
- DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
- DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
- DT_CLK(NULL, "sys_clkin1", "sys_clkin1"),
- DT_CLK(NULL, "sys_clkin2", "sys_clkin2"),
- DT_CLK(NULL, "usb_otg_clkin_ck", "usb_otg_clkin_ck"),
- DT_CLK(NULL, "video1_clkin_ck", "video1_clkin_ck"),
- DT_CLK(NULL, "video1_m2_clkin_ck", "video1_m2_clkin_ck"),
- DT_CLK(NULL, "video2_clkin_ck", "video2_clkin_ck"),
- DT_CLK(NULL, "video2_m2_clkin_ck", "video2_m2_clkin_ck"),
- DT_CLK(NULL, "abe_dpll_sys_clk_mux", "abe_dpll_sys_clk_mux"),
- DT_CLK(NULL, "abe_dpll_bypass_clk_mux", "abe_dpll_bypass_clk_mux"),
- DT_CLK(NULL, "abe_dpll_clk_mux", "abe_dpll_clk_mux"),
- DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
- DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
- DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
- DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
- DT_CLK(NULL, "abe_clk", "abe_clk"),
- DT_CLK(NULL, "aess_fclk", "aess_fclk"),
- DT_CLK(NULL, "abe_giclk_div", "abe_giclk_div"),
- DT_CLK(NULL, "abe_lp_clk_div", "abe_lp_clk_div"),
- DT_CLK(NULL, "abe_sys_clk_div", "abe_sys_clk_div"),
- DT_CLK(NULL, "adc_gfclk_mux", "adc_gfclk_mux"),
- DT_CLK(NULL, "dpll_pcie_ref_ck", "dpll_pcie_ref_ck"),
- DT_CLK(NULL, "dpll_pcie_ref_m2ldo_ck", "dpll_pcie_ref_m2ldo_ck"),
- DT_CLK(NULL, "apll_pcie_ck", "apll_pcie_ck"),
- DT_CLK(NULL, "apll_pcie_clkvcoldo", "apll_pcie_clkvcoldo"),
- DT_CLK(NULL, "apll_pcie_clkvcoldo_div", "apll_pcie_clkvcoldo_div"),
- DT_CLK(NULL, "apll_pcie_m2_ck", "apll_pcie_m2_ck"),
- DT_CLK(NULL, "sys_clk1_dclk_div", "sys_clk1_dclk_div"),
- DT_CLK(NULL, "sys_clk2_dclk_div", "sys_clk2_dclk_div"),
- DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
- DT_CLK(NULL, "per_abe_x1_dclk_div", "per_abe_x1_dclk_div"),
- DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
- DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
- DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
- DT_CLK(NULL, "dpll_core_h12x2_ck", "dpll_core_h12x2_ck"),
- DT_CLK(NULL, "mpu_dpll_hs_clk_div", "mpu_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
- DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
- DT_CLK(NULL, "mpu_dclk_div", "mpu_dclk_div"),
- DT_CLK(NULL, "dsp_dpll_hs_clk_div", "dsp_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_dsp_ck", "dpll_dsp_ck"),
- DT_CLK(NULL, "dpll_dsp_m2_ck", "dpll_dsp_m2_ck"),
- DT_CLK(NULL, "dsp_gclk_div", "dsp_gclk_div"),
- DT_CLK(NULL, "iva_dpll_hs_clk_div", "iva_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
- DT_CLK(NULL, "dpll_iva_m2_ck", "dpll_iva_m2_ck"),
- DT_CLK(NULL, "iva_dclk", "iva_dclk"),
- DT_CLK(NULL, "dpll_gpu_ck", "dpll_gpu_ck"),
- DT_CLK(NULL, "dpll_gpu_m2_ck", "dpll_gpu_m2_ck"),
- DT_CLK(NULL, "gpu_dclk", "gpu_dclk"),
- DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
- DT_CLK(NULL, "core_dpll_out_dclk_div", "core_dpll_out_dclk_div"),
- DT_CLK(NULL, "dpll_ddr_ck", "dpll_ddr_ck"),
- DT_CLK(NULL, "dpll_ddr_m2_ck", "dpll_ddr_m2_ck"),
- DT_CLK(NULL, "emif_phy_dclk_div", "emif_phy_dclk_div"),
- DT_CLK(NULL, "dpll_gmac_ck", "dpll_gmac_ck"),
- DT_CLK(NULL, "dpll_gmac_m2_ck", "dpll_gmac_m2_ck"),
- DT_CLK(NULL, "gmac_250m_dclk_div", "gmac_250m_dclk_div"),
- DT_CLK(NULL, "video2_dclk_div", "video2_dclk_div"),
- DT_CLK(NULL, "video1_dclk_div", "video1_dclk_div"),
- DT_CLK(NULL, "hdmi_dclk_div", "hdmi_dclk_div"),
- DT_CLK(NULL, "per_dpll_hs_clk_div", "per_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
- DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
- DT_CLK(NULL, "func_96m_aon_dclk_div", "func_96m_aon_dclk_div"),
- DT_CLK(NULL, "usb_dpll_hs_clk_div", "usb_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
- DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
- DT_CLK(NULL, "l3init_480m_dclk_div", "l3init_480m_dclk_div"),
- DT_CLK(NULL, "usb_otg_dclk_div", "usb_otg_dclk_div"),
- DT_CLK(NULL, "sata_dclk_div", "sata_dclk_div"),
- DT_CLK(NULL, "dpll_pcie_ref_m2_ck", "dpll_pcie_ref_m2_ck"),
- DT_CLK(NULL, "pcie2_dclk_div", "pcie2_dclk_div"),
- DT_CLK(NULL, "pcie_dclk_div", "pcie_dclk_div"),
- DT_CLK(NULL, "emu_dclk_div", "emu_dclk_div"),
- DT_CLK(NULL, "secure_32k_dclk_div", "secure_32k_dclk_div"),
- DT_CLK(NULL, "eve_dpll_hs_clk_div", "eve_dpll_hs_clk_div"),
- DT_CLK(NULL, "dpll_eve_ck", "dpll_eve_ck"),
- DT_CLK(NULL, "dpll_eve_m2_ck", "dpll_eve_m2_ck"),
- DT_CLK(NULL, "eve_dclk_div", "eve_dclk_div"),
- DT_CLK(NULL, "clkoutmux0_clk_mux", "clkoutmux0_clk_mux"),
- DT_CLK(NULL, "clkoutmux1_clk_mux", "clkoutmux1_clk_mux"),
- DT_CLK(NULL, "clkoutmux2_clk_mux", "clkoutmux2_clk_mux"),
- DT_CLK(NULL, "custefuse_sys_gfclk_div", "custefuse_sys_gfclk_div"),
- DT_CLK(NULL, "dpll_core_h13x2_ck", "dpll_core_h13x2_ck"),
- DT_CLK(NULL, "dpll_core_h14x2_ck", "dpll_core_h14x2_ck"),
- DT_CLK(NULL, "dpll_core_h22x2_ck", "dpll_core_h22x2_ck"),
- DT_CLK(NULL, "dpll_core_h23x2_ck", "dpll_core_h23x2_ck"),
- DT_CLK(NULL, "dpll_core_h24x2_ck", "dpll_core_h24x2_ck"),
- DT_CLK(NULL, "dpll_ddr_x2_ck", "dpll_ddr_x2_ck"),
- DT_CLK(NULL, "dpll_ddr_h11x2_ck", "dpll_ddr_h11x2_ck"),
- DT_CLK(NULL, "dpll_dsp_x2_ck", "dpll_dsp_x2_ck"),
- DT_CLK(NULL, "dpll_dsp_m3x2_ck", "dpll_dsp_m3x2_ck"),
- DT_CLK(NULL, "dpll_gmac_x2_ck", "dpll_gmac_x2_ck"),
- DT_CLK(NULL, "dpll_gmac_h11x2_ck", "dpll_gmac_h11x2_ck"),
- DT_CLK(NULL, "dpll_gmac_h12x2_ck", "dpll_gmac_h12x2_ck"),
- DT_CLK(NULL, "dpll_gmac_h13x2_ck", "dpll_gmac_h13x2_ck"),
- DT_CLK(NULL, "dpll_gmac_m3x2_ck", "dpll_gmac_m3x2_ck"),
- DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
- DT_CLK(NULL, "dpll_per_h11x2_ck", "dpll_per_h11x2_ck"),
- DT_CLK(NULL, "dpll_per_h12x2_ck", "dpll_per_h12x2_ck"),
- DT_CLK(NULL, "dpll_per_h13x2_ck", "dpll_per_h13x2_ck"),
- DT_CLK(NULL, "dpll_per_h14x2_ck", "dpll_per_h14x2_ck"),
- DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
- DT_CLK(NULL, "dpll_usb_clkdcoldo", "dpll_usb_clkdcoldo"),
- DT_CLK(NULL, "eve_clk", "eve_clk"),
- DT_CLK(NULL, "func_128m_clk", "func_128m_clk"),
- DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
- DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
- DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
- DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
- DT_CLK(NULL, "gmii_m_clk_div", "gmii_m_clk_div"),
- DT_CLK(NULL, "hdmi_clk2_div", "hdmi_clk2_div"),
- DT_CLK(NULL, "hdmi_div_clk", "hdmi_div_clk"),
- DT_CLK(NULL, "hdmi_dpll_clk_mux", "hdmi_dpll_clk_mux"),
- DT_CLK(NULL, "l3_iclk_div", "l3_iclk_div"),
- DT_CLK(NULL, "l3init_60m_fclk", "l3init_60m_fclk"),
- DT_CLK(NULL, "l4_root_clk_div", "l4_root_clk_div"),
- DT_CLK(NULL, "mlb_clk", "mlb_clk"),
- DT_CLK(NULL, "mlbp_clk", "mlbp_clk"),
- DT_CLK(NULL, "per_abe_x1_gfclk2_div", "per_abe_x1_gfclk2_div"),
- DT_CLK(NULL, "timer_sys_clk_div", "timer_sys_clk_div"),
- DT_CLK(NULL, "video1_clk2_div", "video1_clk2_div"),
- DT_CLK(NULL, "video1_div_clk", "video1_div_clk"),
- DT_CLK(NULL, "video1_dpll_clk_mux", "video1_dpll_clk_mux"),
- DT_CLK(NULL, "video2_clk2_div", "video2_clk2_div"),
- DT_CLK(NULL, "video2_div_clk", "video2_div_clk"),
- DT_CLK(NULL, "video2_dpll_clk_mux", "video2_dpll_clk_mux"),
- DT_CLK(NULL, "wkupaon_iclk_mux", "wkupaon_iclk_mux"),
- DT_CLK(NULL, "dss_32khz_clk", "dss_32khz_clk"),
- DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
- DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
- DT_CLK(NULL, "dss_hdmi_clk", "dss_hdmi_clk"),
- DT_CLK(NULL, "dss_video1_clk", "dss_video1_clk"),
- DT_CLK(NULL, "dss_video2_clk", "dss_video2_clk"),
- DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
- DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
- DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
- DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
- DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
- DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
- DT_CLK(NULL, "gpio7_dbclk", "gpio7_dbclk"),
- DT_CLK(NULL, "gpio8_dbclk", "gpio8_dbclk"),
- DT_CLK(NULL, "mmc1_clk32k", "mmc1_clk32k"),
- DT_CLK(NULL, "mmc2_clk32k", "mmc2_clk32k"),
- DT_CLK(NULL, "mmc3_clk32k", "mmc3_clk32k"),
- DT_CLK(NULL, "mmc4_clk32k", "mmc4_clk32k"),
- DT_CLK(NULL, "sata_ref_clk", "sata_ref_clk"),
- DT_CLK(NULL, "usb_otg_ss1_refclk960m", "usb_otg_ss1_refclk960m"),
- DT_CLK(NULL, "usb_otg_ss2_refclk960m", "usb_otg_ss2_refclk960m"),
- DT_CLK(NULL, "usb_phy1_always_on_clk32k", "usb_phy1_always_on_clk32k"),
- DT_CLK(NULL, "usb_phy2_always_on_clk32k", "usb_phy2_always_on_clk32k"),
- DT_CLK(NULL, "usb_phy3_always_on_clk32k", "usb_phy3_always_on_clk32k"),
- DT_CLK(NULL, "atl_dpll_clk_mux", "atl_dpll_clk_mux"),
- DT_CLK(NULL, "atl_gfclk_mux", "atl_gfclk_mux"),
- DT_CLK(NULL, "dcan1_sys_clk_mux", "dcan1_sys_clk_mux"),
- DT_CLK(NULL, "gmac_rft_clk_mux", "gmac_rft_clk_mux"),
- DT_CLK(NULL, "gpu_core_gclk_mux", "gpu_core_gclk_mux"),
- DT_CLK(NULL, "gpu_hyd_gclk_mux", "gpu_hyd_gclk_mux"),
- DT_CLK(NULL, "ipu1_gfclk_mux", "ipu1_gfclk_mux"),
- DT_CLK(NULL, "l3instr_ts_gclk_div", "l3instr_ts_gclk_div"),
- DT_CLK(NULL, "mcasp1_ahclkr_mux", "mcasp1_ahclkr_mux"),
- DT_CLK(NULL, "mcasp1_ahclkx_mux", "mcasp1_ahclkx_mux"),
- DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "mcasp1_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp2_ahclkr_mux", "mcasp2_ahclkr_mux"),
- DT_CLK(NULL, "mcasp2_ahclkx_mux", "mcasp2_ahclkx_mux"),
- DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "mcasp2_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp3_ahclkx_mux", "mcasp3_ahclkx_mux"),
- DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "mcasp3_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp4_ahclkx_mux", "mcasp4_ahclkx_mux"),
- DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "mcasp4_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp5_ahclkx_mux", "mcasp5_ahclkx_mux"),
- DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "mcasp5_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp6_ahclkx_mux", "mcasp6_ahclkx_mux"),
- DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"),
- DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"),
- DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"),
- DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"),
- DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"),
- DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"),
- DT_CLK(NULL, "mmc2_fclk_mux", "mmc2_fclk_mux"),
- DT_CLK(NULL, "mmc2_fclk_div", "mmc2_fclk_div"),
- DT_CLK(NULL, "mmc3_gfclk_mux", "mmc3_gfclk_mux"),
- DT_CLK(NULL, "mmc3_gfclk_div", "mmc3_gfclk_div"),
- DT_CLK(NULL, "mmc4_gfclk_mux", "mmc4_gfclk_mux"),
- DT_CLK(NULL, "mmc4_gfclk_div", "mmc4_gfclk_div"),
- DT_CLK(NULL, "qspi_gfclk_mux", "qspi_gfclk_mux"),
- DT_CLK(NULL, "qspi_gfclk_div", "qspi_gfclk_div"),
- DT_CLK(NULL, "timer10_gfclk_mux", "timer10_gfclk_mux"),
- DT_CLK(NULL, "timer11_gfclk_mux", "timer11_gfclk_mux"),
- DT_CLK(NULL, "timer13_gfclk_mux", "timer13_gfclk_mux"),
- DT_CLK(NULL, "timer14_gfclk_mux", "timer14_gfclk_mux"),
- DT_CLK(NULL, "timer15_gfclk_mux", "timer15_gfclk_mux"),
- DT_CLK(NULL, "timer16_gfclk_mux", "timer16_gfclk_mux"),
- DT_CLK(NULL, "timer1_gfclk_mux", "timer1_gfclk_mux"),
- DT_CLK(NULL, "timer2_gfclk_mux", "timer2_gfclk_mux"),
- DT_CLK(NULL, "timer3_gfclk_mux", "timer3_gfclk_mux"),
- DT_CLK(NULL, "timer4_gfclk_mux", "timer4_gfclk_mux"),
- DT_CLK(NULL, "timer5_gfclk_mux", "timer5_gfclk_mux"),
- DT_CLK(NULL, "timer6_gfclk_mux", "timer6_gfclk_mux"),
- DT_CLK(NULL, "timer7_gfclk_mux", "timer7_gfclk_mux"),
- DT_CLK(NULL, "timer8_gfclk_mux", "timer8_gfclk_mux"),
- DT_CLK(NULL, "timer9_gfclk_mux", "timer9_gfclk_mux"),
- DT_CLK(NULL, "uart10_gfclk_mux", "uart10_gfclk_mux"),
- DT_CLK(NULL, "uart1_gfclk_mux", "uart1_gfclk_mux"),
- DT_CLK(NULL, "uart2_gfclk_mux", "uart2_gfclk_mux"),
- DT_CLK(NULL, "uart3_gfclk_mux", "uart3_gfclk_mux"),
- DT_CLK(NULL, "uart4_gfclk_mux", "uart4_gfclk_mux"),
- DT_CLK(NULL, "uart5_gfclk_mux", "uart5_gfclk_mux"),
- DT_CLK(NULL, "uart6_gfclk_mux", "uart6_gfclk_mux"),
- DT_CLK(NULL, "uart7_gfclk_mux", "uart7_gfclk_mux"),
- DT_CLK(NULL, "uart8_gfclk_mux", "uart8_gfclk_mux"),
- DT_CLK(NULL, "uart9_gfclk_mux", "uart9_gfclk_mux"),
- DT_CLK(NULL, "vip1_gclk_mux", "vip1_gclk_mux"),
- DT_CLK(NULL, "vip2_gclk_mux", "vip2_gclk_mux"),
- DT_CLK(NULL, "vip3_gclk_mux", "vip3_gclk_mux"),
- DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
- DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
- DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
- DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
- DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
- DT_CLK(NULL, "uart1_ick", "dummy_ck"),
- DT_CLK(NULL, "uart2_ick", "dummy_ck"),
- DT_CLK(NULL, "uart3_ick", "dummy_ck"),
- DT_CLK(NULL, "uart4_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
- DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
- DT_CLK("omap_wdt", "ick", "dummy_ck"),
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "sys_clkin_ck", "timer_sys_clk_div"),
- DT_CLK("4ae18000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48032000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48034000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48036000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("4803e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48086000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48088000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48820000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48822000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48824000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48826000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("48828000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("4882a000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("4882c000.timer", "timer_sys_ck", "timer_sys_clk_div"),
- DT_CLK("4882e000.timer", "timer_sys_ck", "timer_sys_clk_div"),
DT_CLK(NULL, "sys_clkin", "sys_clkin1"),
- DT_CLK(NULL, "dss_deshdcp_clk", "dss_deshdcp_clk"),
+ DT_CLK(NULL, "atl_dpll_clk_mux", "atl_cm:0000:24"),
+ DT_CLK(NULL, "atl_gfclk_mux", "atl_cm:0000:26"),
+ DT_CLK(NULL, "dcan1_sys_clk_mux", "wkupaon_cm:0068:24"),
+ DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
+ DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
+ DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
+ DT_CLK(NULL, "dss_hdmi_clk", "dss_cm:0000:10"),
+ DT_CLK(NULL, "dss_video1_clk", "dss_cm:0000:12"),
+ DT_CLK(NULL, "dss_video2_clk", "dss_cm:0000:13"),
+ DT_CLK(NULL, "gmac_rft_clk_mux", "l3init_cm:00b0:25"),
+ DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
+ DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0060:8"),
+ DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0068:8"),
+ DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0070:8"),
+ DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0078:8"),
+ DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0080:8"),
+ DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:0110:8"),
+ DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:0118:8"),
+ DT_CLK(NULL, "mcasp1_ahclkr_mux", "ipu_cm:0010:28"),
+ DT_CLK(NULL, "mcasp1_ahclkx_mux", "ipu_cm:0010:24"),
+ DT_CLK(NULL, "mcasp1_aux_gfclk_mux", "ipu_cm:0010:22"),
+ DT_CLK(NULL, "mcasp2_ahclkr_mux", "l4per_cm:0160:28"),
+ DT_CLK(NULL, "mcasp2_ahclkx_mux", "l4per_cm:0160:24"),
+ DT_CLK(NULL, "mcasp2_aux_gfclk_mux", "l4per_cm:0160:22"),
+ DT_CLK(NULL, "mcasp3_ahclkx_mux", "l4per_cm:0168:24"),
+ DT_CLK(NULL, "mcasp3_aux_gfclk_mux", "l4per_cm:0168:22"),
+ DT_CLK(NULL, "mcasp4_ahclkx_mux", "l4per_cm:0198:24"),
+ DT_CLK(NULL, "mcasp4_aux_gfclk_mux", "l4per_cm:0198:22"),
+ DT_CLK(NULL, "mcasp5_ahclkx_mux", "l4per_cm:0178:24"),
+ DT_CLK(NULL, "mcasp5_aux_gfclk_mux", "l4per_cm:0178:22"),
+ DT_CLK(NULL, "mcasp6_ahclkx_mux", "l4per_cm:0204:24"),
+ DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per_cm:0204:22"),
+ DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per_cm:0208:24"),
+ DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per_cm:0208:22"),
+ DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per_cm:0190:22"),
+ DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per_cm:0190:24"),
+ DT_CLK(NULL, "mmc1_clk32k", "l3init_cm:0008:8"),
+ DT_CLK(NULL, "mmc1_fclk_div", "l3init_cm:0008:25"),
+ DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
+ DT_CLK(NULL, "mmc2_clk32k", "l3init_cm:0010:8"),
+ DT_CLK(NULL, "mmc2_fclk_div", "l3init_cm:0010:25"),
+ DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
+ DT_CLK(NULL, "mmc3_clk32k", "l4per_cm:0120:8"),
+ DT_CLK(NULL, "mmc3_gfclk_div", "l4per_cm:0120:25"),
+ DT_CLK(NULL, "mmc3_gfclk_mux", "l4per_cm:0120:24"),
+ DT_CLK(NULL, "mmc4_clk32k", "l4per_cm:0128:8"),
+ DT_CLK(NULL, "mmc4_gfclk_div", "l4per_cm:0128:25"),
+ DT_CLK(NULL, "mmc4_gfclk_mux", "l4per_cm:0128:24"),
+ DT_CLK(NULL, "optfclk_pciephy1_32khz", "l3init_cm:0090:8"),
+ DT_CLK(NULL, "optfclk_pciephy1_clk", "l3init_cm:0090:9"),
+ DT_CLK(NULL, "optfclk_pciephy1_div_clk", "l3init_cm:0090:10"),
+ DT_CLK(NULL, "optfclk_pciephy2_32khz", "l3init_cm:0098:8"),
+ DT_CLK(NULL, "optfclk_pciephy2_clk", "l3init_cm:0098:9"),
+ DT_CLK(NULL, "optfclk_pciephy2_div_clk", "l3init_cm:0098:10"),
+ DT_CLK(NULL, "qspi_gfclk_div", "l4per_cm:0138:25"),
+ DT_CLK(NULL, "qspi_gfclk_mux", "l4per_cm:0138:24"),
+ DT_CLK(NULL, "rmii_50mhz_clk_mux", "l3init_cm:00b0:24"),
+ DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
+ DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0028:24"),
+ DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0030:24"),
+ DT_CLK(NULL, "timer13_gfclk_mux", "l4per_cm:00c8:24"),
+ DT_CLK(NULL, "timer14_gfclk_mux", "l4per_cm:00d0:24"),
+ DT_CLK(NULL, "timer15_gfclk_mux", "l4per_cm:00d8:24"),
+ DT_CLK(NULL, "timer16_gfclk_mux", "l4per_cm:0130:24"),
+ DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
+ DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0038:24"),
+ DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0040:24"),
+ DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0048:24"),
+ DT_CLK(NULL, "timer5_gfclk_mux", "ipu_cm:0018:24"),
+ DT_CLK(NULL, "timer6_gfclk_mux", "ipu_cm:0020:24"),
+ DT_CLK(NULL, "timer7_gfclk_mux", "ipu_cm:0028:24"),
+ DT_CLK(NULL, "timer8_gfclk_mux", "ipu_cm:0030:24"),
+ DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0050:24"),
+ DT_CLK(NULL, "uart10_gfclk_mux", "wkupaon_cm:0060:24"),
+ DT_CLK(NULL, "uart1_gfclk_mux", "l4per_cm:0140:24"),
+ DT_CLK(NULL, "uart2_gfclk_mux", "l4per_cm:0148:24"),
+ DT_CLK(NULL, "uart3_gfclk_mux", "l4per_cm:0150:24"),
+ DT_CLK(NULL, "uart4_gfclk_mux", "l4per_cm:0158:24"),
+ DT_CLK(NULL, "uart5_gfclk_mux", "l4per_cm:0170:24"),
+ DT_CLK(NULL, "uart6_gfclk_mux", "ipu_cm:0040:24"),
+ DT_CLK(NULL, "uart7_gfclk_mux", "l4per_cm:01d0:24"),
+ DT_CLK(NULL, "uart8_gfclk_mux", "l4per_cm:01e0:24"),
+ DT_CLK(NULL, "uart9_gfclk_mux", "l4per_cm:01e8:24"),
+ DT_CLK(NULL, "usb_otg_ss1_refclk960m", "l3init_cm:00d0:8"),
+ DT_CLK(NULL, "usb_otg_ss2_refclk960m", "l3init_cm:0020:8"),
{ .node_name = NULL },
};
@@ -318,6 +830,8 @@ int __init dra7xx_dt_clk_init(void)
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
+
dpll_ck = clk_get_sys(NULL, "dpll_gmac_ck");
rc = clk_set_rate(dpll_ck, DRA7_DPLL_GMAC_DEFFREQ);
if (rc)
diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c
index 52c6efc..f688fdd 100644
--- a/drivers/clk/ti/clk-814x.c
+++ b/drivers/clk/ti/clk-814x.c
@@ -9,23 +9,48 @@
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
#include <linux/of_platform.h>
+#include <dt-bindings/clock/dm814.h>
#include "clock.h"
+static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = {
+ { DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = {
+ { DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
+ { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
+ { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" },
+ { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
+ { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
+ { DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
+ { DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = {
+ { 0x48180500, dm814_default_clkctrl_regs },
+ { 0x48181400, dm814_alwon_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk dm814_clks[] = {
- DT_CLK(NULL, "devosc_ck", "devosc_ck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
- DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
- DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
- DT_CLK(NULL, "sysclk8_ck", "sysclk8_ck"),
- DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
- DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
DT_CLK(NULL, "timer_sys_ck", "devosc_ck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "cpsw_125mhz_gclk", "cpsw_125mhz_gclk"),
- DT_CLK(NULL, "cpsw_cpts_rft_clk", "cpsw_cpts_rft_clk"),
{ .node_name = NULL },
};
@@ -83,6 +108,7 @@ int __init dm814x_dt_clk_init(void)
{
ti_dt_clocks_register(dm814_clks);
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
omap2_clk_enable_init_clocks(NULL, 0);
timer_clocks_initialized = true;
diff --git a/drivers/clk/ti/clk-816x.c b/drivers/clk/ti/clk-816x.c
index 2a5d84f..7d215cd 100644
--- a/drivers/clk/ti/clk-816x.c
+++ b/drivers/clk/ti/clk-816x.c
@@ -13,30 +13,59 @@
#include <linux/list.h>
#include <linux/clk-provider.h>
#include <linux/clk/ti.h>
+#include <dt-bindings/clock/dm816.h>
#include "clock.h"
+static const struct omap_clkctrl_reg_data dm816_default_clkctrl_regs[] __initconst = {
+ { DM816_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { 0 },
+};
+
+static const struct omap_clkctrl_reg_data dm816_alwon_clkctrl_regs[] __initconst = {
+ { DM816_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM816_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM816_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
+ { DM816_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
+ { DM816_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
+ { DM816_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
+ { DM816_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
+ { DM816_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
+ { DM816_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
+ { DM816_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
+ { DM816_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM816_SPINBOX_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM816_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" },
+ { DM816_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" },
+ { DM816_DAVINCI_MDIO_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
+ { DM816_EMAC1_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk24_ck" },
+ { DM816_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk2_ck" },
+ { DM816_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" },
+ { DM816_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM816_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM816_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM816_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { DM816_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" },
+ { 0 },
+};
+
+const struct omap_clkctrl_data dm816_clkctrl_data[] __initconst = {
+ { 0x48180500, dm816_default_clkctrl_regs },
+ { 0x48181400, dm816_alwon_clkctrl_regs },
+ { 0 },
+};
+
static struct ti_dt_clk dm816x_clks[] = {
DT_CLK(NULL, "sys_clkin", "sys_clkin_ck"),
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
- DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
DT_CLK(NULL, "timer_32k_ck", "sysclk18_ck"),
DT_CLK(NULL, "timer_ext_ck", "tclkin_ck"),
- DT_CLK(NULL, "mpu_ck", "mpu_ck"),
- DT_CLK(NULL, "timer1_fck", "timer1_fck"),
- DT_CLK(NULL, "timer2_fck", "timer2_fck"),
- DT_CLK(NULL, "timer3_fck", "timer3_fck"),
- DT_CLK(NULL, "timer4_fck", "timer4_fck"),
- DT_CLK(NULL, "timer5_fck", "timer5_fck"),
- DT_CLK(NULL, "timer6_fck", "timer6_fck"),
- DT_CLK(NULL, "timer7_fck", "timer7_fck"),
- DT_CLK(NULL, "sysclk4_ck", "sysclk4_ck"),
- DT_CLK(NULL, "sysclk5_ck", "sysclk5_ck"),
- DT_CLK(NULL, "sysclk6_ck", "sysclk6_ck"),
- DT_CLK(NULL, "sysclk10_ck", "sysclk10_ck"),
- DT_CLK(NULL, "sysclk18_ck", "sysclk18_ck"),
- DT_CLK(NULL, "sysclk24_ck", "sysclk24_ck"),
- DT_CLK("4a100000.ethernet", "sysclk24_ck", "sysclk24_ck"),
{ .node_name = NULL },
};
@@ -50,6 +79,7 @@ int __init dm816x_dt_clk_init(void)
{
ti_dt_clocks_register(dm816x_clks);
omap2_clk_disable_autoidle_all();
+ ti_clk_add_aliases();
omap2_clk_enable_init_clocks(enable_init_clks,
ARRAY_SIZE(enable_init_clks));
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index e5a1c82..f4d6802 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -108,25 +108,77 @@ void __init ti_dt_clocks_register(struct ti_dt_clk oclks[])
struct device_node *node;
struct clk *clk;
struct of_phandle_args clkspec;
+ char buf[64];
+ char *ptr;
+ char *tags[2];
+ int i;
+ int num_args;
+ int ret;
+ static bool clkctrl_nodes_missing;
+ static bool has_clkctrl_data;
for (c = oclks; c->node_name != NULL; c++) {
- node = of_find_node_by_name(NULL, c->node_name);
+ strcpy(buf, c->node_name);
+ ptr = buf;
+ for (i = 0; i < 2; i++)
+ tags[i] = NULL;
+ num_args = 0;
+ while (*ptr) {
+ if (*ptr == ':') {
+ if (num_args >= 2) {
+ pr_warn("Bad number of tags on %s\n",
+ c->node_name);
+ return;
+ }
+ tags[num_args++] = ptr + 1;
+ *ptr = 0;
+ }
+ ptr++;
+ }
+
+ if (num_args && clkctrl_nodes_missing)
+ continue;
+
+ node = of_find_node_by_name(NULL, buf);
+ if (num_args)
+ node = of_find_node_by_name(node, "clk");
clkspec.np = node;
+ clkspec.args_count = num_args;
+ for (i = 0; i < num_args; i++) {
+ ret = kstrtoint(tags[i], i ? 10 : 16, clkspec.args + i);
+ if (ret) {
+ pr_warn("Bad tag in %s at %d: %s\n",
+ c->node_name, i, tags[i]);
+ return;
+ }
+ }
clk = of_clk_get_from_provider(&clkspec);
if (!IS_ERR(clk)) {
c->lk.clk = clk;
clkdev_add(&c->lk);
} else {
- pr_warn("failed to lookup clock node %s\n",
- c->node_name);
+ if (num_args && !has_clkctrl_data) {
+ if (of_find_compatible_node(NULL, NULL,
+ "ti,clkctrl")) {
+ has_clkctrl_data = true;
+ } else {
+ clkctrl_nodes_missing = true;
+
+ pr_warn("missing clkctrl nodes, please update your dts.\n");
+ continue;
+ }
+ }
+
+ pr_warn("failed to lookup clock node %s, ret=%ld\n",
+ c->node_name, PTR_ERR(clk));
}
}
}
struct clk_init_item {
struct device_node *node;
- struct clk_hw *hw;
+ void *user;
ti_of_clk_init_cb_t func;
struct list_head link;
};
@@ -136,14 +188,14 @@ static LIST_HEAD(retry_list);
/**
* ti_clk_retry_init - retries a failed clock init at later phase
* @node: device not for the clock
- * @hw: partially initialized clk_hw struct for the clock
+ * @user: user data pointer
* @func: init function to be called for the clock
*
* Adds a failed clock init to the retry list. The retry list is parsed
* once all the other clocks have been initialized.
*/
-int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
- ti_of_clk_init_cb_t func)
+int __init ti_clk_retry_init(struct device_node *node, void *user,
+ ti_of_clk_init_cb_t func)
{
struct clk_init_item *retry;
@@ -154,7 +206,7 @@ int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
retry->node = node;
retry->func = func;
- retry->hw = hw;
+ retry->user = user;
list_add(&retry->link, &retry_list);
return 0;
@@ -276,7 +328,7 @@ void ti_dt_clk_init_retry_clks(void)
while (!list_empty(&retry_list) && retries) {
list_for_each_entry_safe(retry, tmp, &retry_list, link) {
pr_debug("retry-init: %s\n", retry->node->name);
- retry->func(retry->hw, retry->node);
+ retry->func(retry->user, retry->node);
list_del(&retry->link);
kfree(retry);
}
@@ -284,141 +336,6 @@ void ti_dt_clk_init_retry_clks(void)
}
}
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
-void __init ti_clk_patch_legacy_clks(struct ti_clk **patch)
-{
- while (*patch) {
- memcpy((*patch)->patch, *patch, sizeof(**patch));
- patch++;
- }
-}
-
-struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
-{
- struct clk *clk;
- struct ti_clk_fixed *fixed;
- struct ti_clk_fixed_factor *fixed_factor;
- struct clk_hw *clk_hw;
- int ret;
-
- if (setup->clk)
- return setup->clk;
-
- switch (setup->type) {
- case TI_CLK_FIXED:
- fixed = setup->data;
-
- clk = clk_register_fixed_rate(NULL, setup->name, NULL, 0,
- fixed->frequency);
- if (!IS_ERR(clk)) {
- ret = ti_clk_add_alias(NULL, clk, setup->name);
- if (ret) {
- clk_unregister(clk);
- clk = ERR_PTR(ret);
- }
- }
- break;
- case TI_CLK_MUX:
- clk = ti_clk_register_mux(setup);
- break;
- case TI_CLK_DIVIDER:
- clk = ti_clk_register_divider(setup);
- break;
- case TI_CLK_COMPOSITE:
- clk = ti_clk_register_composite(setup);
- break;
- case TI_CLK_FIXED_FACTOR:
- fixed_factor = setup->data;
-
- clk = clk_register_fixed_factor(NULL, setup->name,
- fixed_factor->parent,
- 0, fixed_factor->mult,
- fixed_factor->div);
- if (!IS_ERR(clk)) {
- ret = ti_clk_add_alias(NULL, clk, setup->name);
- if (ret) {
- clk_unregister(clk);
- clk = ERR_PTR(ret);
- }
- }
- break;
- case TI_CLK_GATE:
- clk = ti_clk_register_gate(setup);
- break;
- case TI_CLK_DPLL:
- clk = ti_clk_register_dpll(setup);
- break;
- default:
- pr_err("bad type for %s!\n", setup->name);
- clk = ERR_PTR(-EINVAL);
- }
-
- if (!IS_ERR(clk)) {
- setup->clk = clk;
- if (setup->clkdm_name) {
- clk_hw = __clk_get_hw(clk);
- if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) {
- pr_warn("can't setup clkdm for basic clk %s\n",
- setup->name);
- } else {
- to_clk_hw_omap(clk_hw)->clkdm_name =
- setup->clkdm_name;
- omap2_init_clk_clkdm(clk_hw);
- }
- }
- }
-
- return clk;
-}
-
-int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
-{
- struct clk *clk;
- bool retry;
- struct ti_clk_alias *retry_clk;
- struct ti_clk_alias *tmp;
-
- while (clks->clk) {
- clk = ti_clk_register_clk(clks->clk);
- if (IS_ERR(clk)) {
- if (PTR_ERR(clk) == -EAGAIN) {
- list_add(&clks->link, &retry_list);
- } else {
- pr_err("register for %s failed: %ld\n",
- clks->clk->name, PTR_ERR(clk));
- return PTR_ERR(clk);
- }
- }
- clks++;
- }
-
- retry = true;
-
- while (!list_empty(&retry_list) && retry) {
- retry = false;
- list_for_each_entry_safe(retry_clk, tmp, &retry_list, link) {
- pr_debug("retry-init: %s\n", retry_clk->clk->name);
- clk = ti_clk_register_clk(retry_clk->clk);
- if (IS_ERR(clk)) {
- if (PTR_ERR(clk) == -EAGAIN) {
- continue;
- } else {
- pr_err("register for %s failed: %ld\n",
- retry_clk->clk->name,
- PTR_ERR(clk));
- return PTR_ERR(clk);
- }
- } else {
- retry = true;
- list_del(&retry_clk->link);
- }
- }
- }
-
- return 0;
-}
-#endif
-
static const struct of_device_id simple_clk_match_table[] __initconst = {
{ .compatible = "fixed-clock" },
{ .compatible = "fixed-factor-clock" },
diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c
index 53e71d0..afa0d6b 100644
--- a/drivers/clk/ti/clkctrl.c
+++ b/drivers/clk/ti/clkctrl.c
@@ -21,6 +21,7 @@
#include <linux/of_address.h>
#include <linux/clk/ti.h>
#include <linux/delay.h>
+#include <linux/timekeeping.h>
#include "clock.h"
#define NO_IDLEST 0x1
@@ -46,6 +47,7 @@ static bool _early_timeout = true;
struct omap_clkctrl_provider {
void __iomem *base;
struct list_head clocks;
+ char *clkdm_name;
};
struct omap_clkctrl_clk {
@@ -89,7 +91,18 @@ static bool _omap4_is_ready(u32 val)
static bool _omap4_is_timeout(union omap4_timeout *time, u32 timeout)
{
- if (unlikely(_early_timeout)) {
+ /*
+ * There are two special cases where ktime_to_ns() can't be
+ * used to track the timeouts. First one is during early boot
+ * when the timers haven't been initialized yet. The second
+ * one is during suspend-resume cycle while timekeeping is
+ * being suspended / resumed. Clocksource for the system
+ * can be from a timer that requires pm_runtime access, which
+ * will eventually bring us here with timekeeping_suspended,
+ * during both suspend entry and resume paths. This happens
+ * at least on am43xx platform.
+ */
+ if (unlikely(_early_timeout || timekeeping_suspended)) {
if (time->cycles++ < timeout) {
udelay(1);
return false;
@@ -208,6 +221,7 @@ static const struct clk_ops omap4_clkctrl_clk_ops = {
.enable = _omap4_clkctrl_clk_enable,
.disable = _omap4_clkctrl_clk_disable,
.is_enabled = _omap4_clkctrl_clk_is_enabled,
+ .init = omap2_init_clk_clkdm,
};
static struct clk_hw *_ti_omap4_clkctrl_xlate(struct of_phandle_args *clkspec,
@@ -321,6 +335,9 @@ _ti_clkctrl_setup_mux(struct omap_clkctrl_provider *provider,
}
mux->mask = num_parents;
+ if (!(mux->flags & CLK_MUX_INDEX_ONE))
+ mux->mask--;
+
mux->mask = (1 << fls(mux->mask)) - 1;
mux->shift = data->bit;
@@ -340,6 +357,7 @@ _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
{
struct clk_omap_divider *div;
const struct omap_clkctrl_div_data *div_data = data->data;
+ u8 div_flags = 0;
div = kzalloc(sizeof(*div), GFP_KERNEL);
if (!div)
@@ -347,12 +365,16 @@ _ti_clkctrl_setup_div(struct omap_clkctrl_provider *provider,
div->reg.ptr = reg;
div->shift = data->bit;
+ div->flags = div_data->flags;
- if (ti_clk_parse_divider_data((int *)div_data->dividers,
- div_data->max_div, 0, 0,
+ if (div->flags & CLK_DIVIDER_POWER_OF_TWO)
+ div_flags |= CLKF_INDEX_POWER_OF_TWO;
+
+ if (ti_clk_parse_divider_data((int *)div_data->dividers, 0,
+ div_data->max_div, div_flags,
&div->width, &div->table)) {
- pr_err("%s: Data parsing for %s:%04x:%d failed\n", __func__,
- node->name, offset, data->bit);
+ pr_err("%s: Data parsing for %pOF:%04x:%d failed\n", __func__,
+ node, offset, data->bit);
kfree(div);
return;
}
@@ -400,6 +422,12 @@ _ti_clkctrl_setup_subclks(struct omap_clkctrl_provider *provider,
}
}
+static void __init _clkctrl_add_provider(void *data,
+ struct device_node *np)
+{
+ of_clk_add_hw_provider(np, _ti_omap4_clkctrl_xlate, data);
+}
+
static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
{
struct omap_clkctrl_provider *provider;
@@ -411,6 +439,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
struct omap_clkctrl_clk *clkctrl_clk;
const __be32 *addrp;
u32 addr;
+ int ret;
addrp = of_get_address(node, 0, NULL, NULL);
addr = (u32)of_translate_address(node, addrp);
@@ -419,6 +448,31 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
if (of_machine_is_compatible("ti,omap4"))
data = omap4_clkctrl_data;
#endif
+#ifdef CONFIG_SOC_OMAP5
+ if (of_machine_is_compatible("ti,omap5"))
+ data = omap5_clkctrl_data;
+#endif
+#ifdef CONFIG_SOC_DRA7XX
+ if (of_machine_is_compatible("ti,dra7"))
+ data = dra7_clkctrl_data;
+#endif
+#ifdef CONFIG_SOC_AM33XX
+ if (of_machine_is_compatible("ti,am33xx"))
+ data = am3_clkctrl_data;
+#endif
+#ifdef CONFIG_SOC_AM43XX
+ if (of_machine_is_compatible("ti,am4372"))
+ data = am4_clkctrl_data;
+ if (of_machine_is_compatible("ti,am438x"))
+ data = am438x_clkctrl_data;
+#endif
+#ifdef CONFIG_SOC_TI81XX
+ if (of_machine_is_compatible("ti,dm814"))
+ data = dm814_clkctrl_data;
+
+ if (of_machine_is_compatible("ti,dm816"))
+ data = dm816_clkctrl_data;
+#endif
while (data->addr) {
if (addr == data->addr)
@@ -428,7 +482,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
}
if (!data->addr) {
- pr_err("%s not found from clkctrl data.\n", node->name);
+ pr_err("%pOF not found from clkctrl data.\n", node);
return;
}
@@ -438,6 +492,21 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
provider->base = of_iomap(node, 0);
+ provider->clkdm_name = kmalloc(strlen(node->parent->name) + 3,
+ GFP_KERNEL);
+ if (!provider->clkdm_name) {
+ kfree(provider);
+ return;
+ }
+
+ /*
+ * Create default clkdm name, replace _cm from end of parent node
+ * name with _clkdm
+ */
+ strcpy(provider->clkdm_name, node->parent->name);
+ provider->clkdm_name[strlen(provider->clkdm_name) - 2] = 0;
+ strcat(provider->clkdm_name, "clkdm");
+
INIT_LIST_HEAD(&provider->clocks);
/* Generate clocks */
@@ -460,6 +529,11 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
if (reg_data->flags & CLKF_NO_IDLEST)
hw->flags |= NO_IDLEST;
+ if (reg_data->clkdm_name)
+ hw->clkdm_name = reg_data->clkdm_name;
+ else
+ hw->clkdm_name = provider->clkdm_name;
+
init.parent_names = ®_data->parent;
init.num_parents = 1;
init.flags = 0;
@@ -485,7 +559,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
reg_data++;
}
- of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
+ ret = of_clk_add_hw_provider(node, _ti_omap4_clkctrl_xlate, provider);
+ if (ret == -EPROBE_DEFER)
+ ti_clk_retry_init(node, provider, _clkctrl_add_provider);
+
return;
cleanup:
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 561dbe9..d9b43bf 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -92,17 +92,6 @@ struct ti_clk {
struct clk *clk;
};
-struct ti_clk_alias {
- struct ti_clk *clk;
- struct clk_lookup lk;
- struct list_head link;
-};
-
-struct ti_clk_fixed {
- u32 frequency;
- u16 flags;
-};
-
struct ti_clk_mux {
u8 bit_shift;
int num_parents;
@@ -123,13 +112,6 @@ struct ti_clk_divider {
u16 flags;
};
-struct ti_clk_fixed_factor {
- const char *parent;
- u16 div;
- u16 mult;
- u16 flags;
-};
-
struct ti_clk_gate {
const char *parent;
u8 bit_shift;
@@ -138,44 +120,6 @@ struct ti_clk_gate {
u16 flags;
};
-struct ti_clk_composite {
- struct ti_clk_divider *divider;
- struct ti_clk_mux *mux;
- struct ti_clk_gate *gate;
- u16 flags;
-};
-
-struct ti_clk_clkdm_gate {
- const char *parent;
- u16 flags;
-};
-
-struct ti_clk_dpll {
- int num_parents;
- u16 control_reg;
- u16 idlest_reg;
- u16 autoidle_reg;
- u16 mult_div1_reg;
- u8 module;
- const char **parents;
- u16 flags;
- u8 modes;
- u32 mult_mask;
- u32 div1_mask;
- u32 enable_mask;
- u32 autoidle_mask;
- u32 freqsel_mask;
- u32 idlest_mask;
- u32 dco_mask;
- u32 sddiv_mask;
- u16 max_multiplier;
- u16 max_divider;
- u8 min_divider;
- u8 auto_recal_bit;
- u8 recal_en_bit;
- u8 recal_st_bit;
-};
-
/* Composite clock component types */
enum {
CLK_COMPONENT_TYPE_GATE = 0,
@@ -207,6 +151,7 @@ struct ti_dt_clk {
struct omap_clkctrl_div_data {
const int *dividers;
int max_div;
+ u32 flags;
};
struct omap_clkctrl_bit_data {
@@ -221,6 +166,7 @@ struct omap_clkctrl_reg_data {
const struct omap_clkctrl_bit_data *bit_data;
u16 flags;
const char *parent;
+ const char *clkdm_name;
};
struct omap_clkctrl_data {
@@ -229,40 +175,35 @@ struct omap_clkctrl_data {
};
extern const struct omap_clkctrl_data omap4_clkctrl_data[];
+extern const struct omap_clkctrl_data omap5_clkctrl_data[];
+extern const struct omap_clkctrl_data dra7_clkctrl_data[];
+extern const struct omap_clkctrl_data am3_clkctrl_data[];
+extern const struct omap_clkctrl_data am4_clkctrl_data[];
+extern const struct omap_clkctrl_data am438x_clkctrl_data[];
+extern const struct omap_clkctrl_data dm814_clkctrl_data[];
+extern const struct omap_clkctrl_data dm816_clkctrl_data[];
#define CLKF_SW_SUP BIT(0)
#define CLKF_HW_SUP BIT(1)
#define CLKF_NO_IDLEST BIT(2)
-typedef void (*ti_of_clk_init_cb_t)(struct clk_hw *, struct device_node *);
+typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
-struct clk *ti_clk_register_gate(struct ti_clk *setup);
-struct clk *ti_clk_register_interface(struct ti_clk *setup);
-struct clk *ti_clk_register_mux(struct ti_clk *setup);
-struct clk *ti_clk_register_divider(struct ti_clk *setup);
-struct clk *ti_clk_register_composite(struct ti_clk *setup);
-struct clk *ti_clk_register_dpll(struct ti_clk *setup);
struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
const char *con);
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
void ti_clk_add_aliases(void);
-struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
-struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
u8 flags, u8 *width,
const struct clk_div_table **table);
-void ti_clk_patch_legacy_clks(struct ti_clk **patch);
-struct clk *ti_clk_register_clk(struct ti_clk *setup);
-int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
-
int ti_clk_get_reg_addr(struct device_node *node, int index,
struct clk_omap_reg *reg);
void ti_dt_clocks_register(struct ti_dt_clk *oclks);
-int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
+int ti_clk_retry_init(struct device_node *node, void *user,
ti_of_clk_init_cb_t func);
int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index beea894..030e8b2 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -116,54 +116,10 @@ static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
-struct clk *ti_clk_register_composite(struct ti_clk *setup)
-{
- struct ti_clk_composite *comp;
- struct clk_hw *gate;
- struct clk_hw *mux;
- struct clk_hw *div;
- int num_parents = 1;
- const char * const *parent_names = NULL;
- struct clk *clk;
- int ret;
-
- comp = setup->data;
-
- div = ti_clk_build_component_div(comp->divider);
- gate = ti_clk_build_component_gate(comp->gate);
- mux = ti_clk_build_component_mux(comp->mux);
-
- if (div)
- parent_names = &comp->divider->parent;
-
- if (gate)
- parent_names = &comp->gate->parent;
-
- if (mux) {
- num_parents = comp->mux->num_parents;
- parent_names = comp->mux->parents;
- }
-
- clk = clk_register_composite(NULL, setup->name,
- parent_names, num_parents, mux,
- &ti_clk_mux_ops, div,
- &ti_composite_divider_ops, gate,
- &ti_composite_gate_ops, 0);
-
- ret = ti_clk_add_alias(NULL, clk, setup->name);
- if (ret) {
- clk_unregister(clk);
- return ERR_PTR(ret);
- }
-
- return clk;
-}
-#endif
-
-static void __init _register_composite(struct clk_hw *hw,
+static void __init _register_composite(void *user,
struct device_node *node)
{
+ struct clk_hw *hw = user;
struct clk *clk;
struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
struct component_clk *comp;
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index d4e4444..7d33ca9 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -152,9 +152,10 @@ static const struct clk_ops dpll_x2_ck_ops = {
* clk-bypass is missing), the clock is added to retry list and
* the initialization is retried on later stage.
*/
-static void __init _register_dpll(struct clk_hw *hw,
+static void __init _register_dpll(void *user,
struct device_node *node)
{
+ struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *dd = clk_hw->dpll_data;
struct clk *clk;
@@ -202,96 +203,6 @@ static void __init _register_dpll(struct clk_hw *hw,
kfree(clk_hw);
}
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
-void _get_reg(u8 module, u16 offset, struct clk_omap_reg *reg)
-{
- reg->index = module;
- reg->offset = offset;
-}
-
-struct clk *ti_clk_register_dpll(struct ti_clk *setup)
-{
- struct clk_hw_omap *clk_hw;
- struct clk_init_data init = { NULL };
- struct dpll_data *dd;
- struct clk *clk;
- struct ti_clk_dpll *dpll;
- const struct clk_ops *ops = &omap3_dpll_ck_ops;
- struct clk *clk_ref;
- struct clk *clk_bypass;
-
- dpll = setup->data;
-
- if (dpll->num_parents < 2)
- return ERR_PTR(-EINVAL);
-
- clk_ref = clk_get_sys(NULL, dpll->parents[0]);
- clk_bypass = clk_get_sys(NULL, dpll->parents[1]);
-
- if (IS_ERR_OR_NULL(clk_ref) || IS_ERR_OR_NULL(clk_bypass))
- return ERR_PTR(-EAGAIN);
-
- dd = kzalloc(sizeof(*dd), GFP_KERNEL);
- clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
- if (!dd || !clk_hw) {
- clk = ERR_PTR(-ENOMEM);
- goto cleanup;
- }
-
- clk_hw->dpll_data = dd;
- clk_hw->ops = &clkhwops_omap3_dpll;
- clk_hw->hw.init = &init;
-
- init.name = setup->name;
- init.ops = ops;
-
- init.num_parents = dpll->num_parents;
- init.parent_names = dpll->parents;
-
- _get_reg(dpll->module, dpll->control_reg, &dd->control_reg);
- _get_reg(dpll->module, dpll->idlest_reg, &dd->idlest_reg);
- _get_reg(dpll->module, dpll->mult_div1_reg, &dd->mult_div1_reg);
- _get_reg(dpll->module, dpll->autoidle_reg, &dd->autoidle_reg);
-
- dd->modes = dpll->modes;
- dd->div1_mask = dpll->div1_mask;
- dd->idlest_mask = dpll->idlest_mask;
- dd->mult_mask = dpll->mult_mask;
- dd->autoidle_mask = dpll->autoidle_mask;
- dd->enable_mask = dpll->enable_mask;
- dd->sddiv_mask = dpll->sddiv_mask;
- dd->dco_mask = dpll->dco_mask;
- dd->max_divider = dpll->max_divider;
- dd->min_divider = dpll->min_divider;
- dd->max_multiplier = dpll->max_multiplier;
- dd->auto_recal_bit = dpll->auto_recal_bit;
- dd->recal_en_bit = dpll->recal_en_bit;
- dd->recal_st_bit = dpll->recal_st_bit;
-
- dd->clk_ref = __clk_get_hw(clk_ref);
- dd->clk_bypass = __clk_get_hw(clk_bypass);
-
- if (dpll->flags & CLKF_CORE)
- ops = &omap3_dpll_core_ck_ops;
-
- if (dpll->flags & CLKF_PER)
- ops = &omap3_dpll_per_ck_ops;
-
- if (dpll->flags & CLKF_J_TYPE)
- dd->flags |= DPLL_J_TYPE;
-
- clk = ti_clk_register(NULL, &clk_hw->hw, setup->name);
-
- if (!IS_ERR(clk))
- return clk;
-
-cleanup:
- kfree(dd);
- kfree(clk_hw);
- return clk;
-}
-#endif
-
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM33XX) || \
defined(CONFIG_SOC_AM43XX)
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index 7151ec3..935b2de 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -128,53 +128,6 @@ static struct clk *_register_gate(struct device *dev, const char *name,
return clk;
}
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
-struct clk *ti_clk_register_gate(struct ti_clk *setup)
-{
- const struct clk_ops *ops = &omap_gate_clk_ops;
- const struct clk_hw_omap_ops *hw_ops = NULL;
- struct clk_omap_reg reg;
- u32 flags = 0;
- u8 clk_gate_flags = 0;
- struct ti_clk_gate *gate;
-
- gate = setup->data;
-
- if (gate->flags & CLKF_INTERFACE)
- return ti_clk_register_interface(setup);
-
- if (gate->flags & CLKF_SET_RATE_PARENT)
- flags |= CLK_SET_RATE_PARENT;
-
- if (gate->flags & CLKF_SET_BIT_TO_DISABLE)
- clk_gate_flags |= INVERT_ENABLE;
-
- if (gate->flags & CLKF_HSDIV) {
- ops = &omap_gate_clk_hsdiv_restore_ops;
- hw_ops = &clkhwops_wait;
- }
-
- if (gate->flags & CLKF_DSS)
- hw_ops = &clkhwops_omap3430es2_dss_usbhost_wait;
-
- if (gate->flags & CLKF_WAIT)
- hw_ops = &clkhwops_wait;
-
- if (gate->flags & CLKF_CLKDM)
- ops = &omap_gate_clkdm_clk_ops;
-
- if (gate->flags & CLKF_AM35XX)
- hw_ops = &clkhwops_am35xx_ipss_module_wait;
-
- reg.index = gate->module;
- reg.offset = gate->reg;
- reg.ptr = NULL;
-
- return _register_gate(NULL, setup->name, gate->parent, flags,
- ®, gate->bit_shift,
- clk_gate_flags, ops, hw_ops);
-}
-
struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
{
struct clk_hw_omap *gate;
@@ -204,7 +157,6 @@ struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
return &gate->hw;
}
-#endif
static void __init _of_ti_gate_clk_setup(struct device_node *node,
const struct clk_ops *ops,
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index 62cf50c..41ae702 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -67,38 +67,6 @@ static struct clk *_register_interface(struct device *dev, const char *name,
return clk;
}
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
-struct clk *ti_clk_register_interface(struct ti_clk *setup)
-{
- const struct clk_hw_omap_ops *ops = &clkhwops_iclk_wait;
- struct clk_omap_reg reg;
- struct ti_clk_gate *gate;
-
- gate = setup->data;
- reg.index = gate->module;
- reg.offset = gate->reg;
- reg.ptr = NULL;
-
- if (gate->flags & CLKF_NO_WAIT)
- ops = &clkhwops_iclk;
-
- if (gate->flags & CLKF_HSOTGUSB)
- ops = &clkhwops_omap3430es2_iclk_hsotgusb_wait;
-
- if (gate->flags & CLKF_DSS)
- ops = &clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-
- if (gate->flags & CLKF_SSI)
- ops = &clkhwops_omap3430es2_iclk_ssi_wait;
-
- if (gate->flags & CLKF_AM35XX)
- ops = &clkhwops_am35xx_ipss_wait;
-
- return _register_interface(NULL, setup->name, gate->parent,
- ®, gate->bit_shift, ops);
-}
-#endif
-
static void __init _of_ti_interface_clk_setup(struct device_node *node,
const struct clk_hw_omap_ops *ops)
{
diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h
new file mode 100644
index 0000000..b396f00
--- /dev/null
+++ b/include/dt-bindings/clock/am3.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM3_H
+#define __DT_BINDINGS_CLK_AM3_H
+
+#define AM3_CLKCTRL_OFFSET 0x0
+#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
+
+/* l4_per clocks */
+#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
+#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
+#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
+#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
+#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
+#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
+#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
+#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
+#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
+#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
+#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38)
+#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c)
+#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
+#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44)
+#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48)
+#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c)
+#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50)
+#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60)
+#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68)
+#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c)
+#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70)
+#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74)
+#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78)
+#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c)
+#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80)
+#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84)
+#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88)
+#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
+#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
+#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0)
+#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac)
+#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0)
+#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4)
+#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc)
+#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0)
+#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4)
+#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc)
+#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4)
+#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8)
+#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc)
+#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0)
+#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8)
+#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec)
+#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0)
+#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4)
+#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8)
+#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc)
+#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100)
+#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c)
+#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110)
+#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120)
+#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130)
+#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c)
+
+/* l4_wkup clocks */
+#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4
+#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
+#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
+#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
+#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
+#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
+#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
+#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
+#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
+#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
+#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
+#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
+#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
+#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
+
+/* mpu clocks */
+#define AM3_MPU_CLKCTRL_OFFSET 0x4
+#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET)
+#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
+
+/* l4_rtc clocks */
+#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
+
+/* gfx_l3 clocks */
+#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4
+#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
+#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
+
+/* l4_cefuse clocks */
+#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20
+#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
+#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
+
+#endif
diff --git a/include/dt-bindings/clock/am4.h b/include/dt-bindings/clock/am4.h
new file mode 100644
index 0000000..d21df00
--- /dev/null
+++ b/include/dt-bindings/clock/am4.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_AM4_H
+#define __DT_BINDINGS_CLK_AM4_H
+
+#define AM4_CLKCTRL_OFFSET 0x20
+#define AM4_CLKCTRL_INDEX(offset) ((offset) - AM4_CLKCTRL_OFFSET)
+
+/* l4_wkup clocks */
+#define AM4_ADC_TSC_CLKCTRL AM4_CLKCTRL_INDEX(0x120)
+#define AM4_L4_WKUP_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
+#define AM4_WKUP_M3_CLKCTRL AM4_CLKCTRL_INDEX(0x228)
+#define AM4_COUNTER_32K_CLKCTRL AM4_CLKCTRL_INDEX(0x230)
+#define AM4_TIMER1_CLKCTRL AM4_CLKCTRL_INDEX(0x328)
+#define AM4_WD_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x338)
+#define AM4_I2C1_CLKCTRL AM4_CLKCTRL_INDEX(0x340)
+#define AM4_UART1_CLKCTRL AM4_CLKCTRL_INDEX(0x348)
+#define AM4_SMARTREFLEX0_CLKCTRL AM4_CLKCTRL_INDEX(0x350)
+#define AM4_SMARTREFLEX1_CLKCTRL AM4_CLKCTRL_INDEX(0x358)
+#define AM4_CONTROL_CLKCTRL AM4_CLKCTRL_INDEX(0x360)
+#define AM4_GPIO1_CLKCTRL AM4_CLKCTRL_INDEX(0x368)
+
+/* mpu clocks */
+#define AM4_MPU_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
+
+/* gfx_l3 clocks */
+#define AM4_GFX_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
+
+/* l4_rtc clocks */
+#define AM4_RTC_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
+
+/* l4_per clocks */
+#define AM4_L3_MAIN_CLKCTRL AM4_CLKCTRL_INDEX(0x20)
+#define AM4_AES_CLKCTRL AM4_CLKCTRL_INDEX(0x28)
+#define AM4_DES_CLKCTRL AM4_CLKCTRL_INDEX(0x30)
+#define AM4_L3_INSTR_CLKCTRL AM4_CLKCTRL_INDEX(0x40)
+#define AM4_OCMCRAM_CLKCTRL AM4_CLKCTRL_INDEX(0x50)
+#define AM4_SHAM_CLKCTRL AM4_CLKCTRL_INDEX(0x58)
+#define AM4_VPFE0_CLKCTRL AM4_CLKCTRL_INDEX(0x68)
+#define AM4_VPFE1_CLKCTRL AM4_CLKCTRL_INDEX(0x70)
+#define AM4_TPCC_CLKCTRL AM4_CLKCTRL_INDEX(0x78)
+#define AM4_TPTC0_CLKCTRL AM4_CLKCTRL_INDEX(0x80)
+#define AM4_TPTC1_CLKCTRL AM4_CLKCTRL_INDEX(0x88)
+#define AM4_TPTC2_CLKCTRL AM4_CLKCTRL_INDEX(0x90)
+#define AM4_L4_HS_CLKCTRL AM4_CLKCTRL_INDEX(0xa0)
+#define AM4_GPMC_CLKCTRL AM4_CLKCTRL_INDEX(0x220)
+#define AM4_MCASP0_CLKCTRL AM4_CLKCTRL_INDEX(0x238)
+#define AM4_MCASP1_CLKCTRL AM4_CLKCTRL_INDEX(0x240)
+#define AM4_MMC3_CLKCTRL AM4_CLKCTRL_INDEX(0x248)
+#define AM4_QSPI_CLKCTRL AM4_CLKCTRL_INDEX(0x258)
+#define AM4_USB_OTG_SS0_CLKCTRL AM4_CLKCTRL_INDEX(0x260)
+#define AM4_USB_OTG_SS1_CLKCTRL AM4_CLKCTRL_INDEX(0x268)
+#define AM4_PRUSS_CLKCTRL AM4_CLKCTRL_INDEX(0x320)
+#define AM4_L4_LS_CLKCTRL AM4_CLKCTRL_INDEX(0x420)
+#define AM4_D_CAN0_CLKCTRL AM4_CLKCTRL_INDEX(0x428)
+#define AM4_D_CAN1_CLKCTRL AM4_CLKCTRL_INDEX(0x430)
+#define AM4_EPWMSS0_CLKCTRL AM4_CLKCTRL_INDEX(0x438)
+#define AM4_EPWMSS1_CLKCTRL AM4_CLKCTRL_INDEX(0x440)
+#define AM4_EPWMSS2_CLKCTRL AM4_CLKCTRL_INDEX(0x448)
+#define AM4_EPWMSS3_CLKCTRL AM4_CLKCTRL_INDEX(0x450)
+#define AM4_EPWMSS4_CLKCTRL AM4_CLKCTRL_INDEX(0x458)
+#define AM4_EPWMSS5_CLKCTRL AM4_CLKCTRL_INDEX(0x460)
+#define AM4_ELM_CLKCTRL AM4_CLKCTRL_INDEX(0x468)
+#define AM4_GPIO2_CLKCTRL AM4_CLKCTRL_INDEX(0x478)
+#define AM4_GPIO3_CLKCTRL AM4_CLKCTRL_INDEX(0x480)
+#define AM4_GPIO4_CLKCTRL AM4_CLKCTRL_INDEX(0x488)
+#define AM4_GPIO5_CLKCTRL AM4_CLKCTRL_INDEX(0x490)
+#define AM4_GPIO6_CLKCTRL AM4_CLKCTRL_INDEX(0x498)
+#define AM4_HDQ1W_CLKCTRL AM4_CLKCTRL_INDEX(0x4a0)
+#define AM4_I2C2_CLKCTRL AM4_CLKCTRL_INDEX(0x4a8)
+#define AM4_I2C3_CLKCTRL AM4_CLKCTRL_INDEX(0x4b0)
+#define AM4_MAILBOX_CLKCTRL AM4_CLKCTRL_INDEX(0x4b8)
+#define AM4_MMC1_CLKCTRL AM4_CLKCTRL_INDEX(0x4c0)
+#define AM4_MMC2_CLKCTRL AM4_CLKCTRL_INDEX(0x4c8)
+#define AM4_RNG_CLKCTRL AM4_CLKCTRL_INDEX(0x4e0)
+#define AM4_SPI0_CLKCTRL AM4_CLKCTRL_INDEX(0x500)
+#define AM4_SPI1_CLKCTRL AM4_CLKCTRL_INDEX(0x508)
+#define AM4_SPI2_CLKCTRL AM4_CLKCTRL_INDEX(0x510)
+#define AM4_SPI3_CLKCTRL AM4_CLKCTRL_INDEX(0x518)
+#define AM4_SPI4_CLKCTRL AM4_CLKCTRL_INDEX(0x520)
+#define AM4_SPINLOCK_CLKCTRL AM4_CLKCTRL_INDEX(0x528)
+#define AM4_TIMER2_CLKCTRL AM4_CLKCTRL_INDEX(0x530)
+#define AM4_TIMER3_CLKCTRL AM4_CLKCTRL_INDEX(0x538)
+#define AM4_TIMER4_CLKCTRL AM4_CLKCTRL_INDEX(0x540)
+#define AM4_TIMER5_CLKCTRL AM4_CLKCTRL_INDEX(0x548)
+#define AM4_TIMER6_CLKCTRL AM4_CLKCTRL_INDEX(0x550)
+#define AM4_TIMER7_CLKCTRL AM4_CLKCTRL_INDEX(0x558)
+#define AM4_TIMER8_CLKCTRL AM4_CLKCTRL_INDEX(0x560)
+#define AM4_TIMER9_CLKCTRL AM4_CLKCTRL_INDEX(0x568)
+#define AM4_TIMER10_CLKCTRL AM4_CLKCTRL_INDEX(0x570)
+#define AM4_TIMER11_CLKCTRL AM4_CLKCTRL_INDEX(0x578)
+#define AM4_UART2_CLKCTRL AM4_CLKCTRL_INDEX(0x580)
+#define AM4_UART3_CLKCTRL AM4_CLKCTRL_INDEX(0x588)
+#define AM4_UART4_CLKCTRL AM4_CLKCTRL_INDEX(0x590)
+#define AM4_UART5_CLKCTRL AM4_CLKCTRL_INDEX(0x598)
+#define AM4_UART6_CLKCTRL AM4_CLKCTRL_INDEX(0x5a0)
+#define AM4_OCP2SCP0_CLKCTRL AM4_CLKCTRL_INDEX(0x5b8)
+#define AM4_OCP2SCP1_CLKCTRL AM4_CLKCTRL_INDEX(0x5c0)
+#define AM4_EMIF_CLKCTRL AM4_CLKCTRL_INDEX(0x720)
+#define AM4_DSS_CORE_CLKCTRL AM4_CLKCTRL_INDEX(0xa20)
+#define AM4_CPGMAC0_CLKCTRL AM4_CLKCTRL_INDEX(0xb20)
+
+#endif
diff --git a/include/dt-bindings/clock/dm814.h b/include/dt-bindings/clock/dm814.h
new file mode 100644
index 0000000..0e7099a
--- /dev/null
+++ b/include/dt-bindings/clock/dm814.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DM814_H
+#define __DT_BINDINGS_CLK_DM814_H
+
+#define DM814_CLKCTRL_OFFSET 0x0
+#define DM814_CLKCTRL_INDEX(offset) ((offset) - DM814_CLKCTRL_OFFSET)
+
+/* default clocks */
+#define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
+
+/* alwon clocks */
+#define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
+#define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
+#define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
+#define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
+#define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
+#define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
+#define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
+#define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
+#define DM814_MCSPI1_CLKCTRL DM814_CLKCTRL_INDEX(0x190)
+#define DM814_GPMC_CLKCTRL DM814_CLKCTRL_INDEX(0x1d0)
+#define DM814_CPGMAC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1d4)
+#define DM814_MPU_CLKCTRL DM814_CLKCTRL_INDEX(0x1dc)
+#define DM814_RTC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f0)
+#define DM814_TPCC_CLKCTRL DM814_CLKCTRL_INDEX(0x1f4)
+#define DM814_TPTC0_CLKCTRL DM814_CLKCTRL_INDEX(0x1f8)
+#define DM814_TPTC1_CLKCTRL DM814_CLKCTRL_INDEX(0x1fc)
+#define DM814_TPTC2_CLKCTRL DM814_CLKCTRL_INDEX(0x200)
+#define DM814_TPTC3_CLKCTRL DM814_CLKCTRL_INDEX(0x204)
+#define DM814_MMC1_CLKCTRL DM814_CLKCTRL_INDEX(0x21c)
+#define DM814_MMC2_CLKCTRL DM814_CLKCTRL_INDEX(0x220)
+#define DM814_MMC3_CLKCTRL DM814_CLKCTRL_INDEX(0x224)
+
+#endif
diff --git a/include/dt-bindings/clock/dm816.h b/include/dt-bindings/clock/dm816.h
new file mode 100644
index 0000000..69e8a36
--- /dev/null
+++ b/include/dt-bindings/clock/dm816.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DM816_H
+#define __DT_BINDINGS_CLK_DM816_H
+
+#define DM816_CLKCTRL_OFFSET 0x0
+#define DM816_CLKCTRL_INDEX(offset) ((offset) - DM816_CLKCTRL_OFFSET)
+
+/* default clocks */
+#define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
+
+/* alwon clocks */
+#define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
+#define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
+#define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
+#define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
+#define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
+#define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
+#define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
+#define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
+#define DM816_TIMER2_CLKCTRL DM816_CLKCTRL_INDEX(0x174)
+#define DM816_TIMER3_CLKCTRL DM816_CLKCTRL_INDEX(0x178)
+#define DM816_TIMER4_CLKCTRL DM816_CLKCTRL_INDEX(0x17c)
+#define DM816_TIMER5_CLKCTRL DM816_CLKCTRL_INDEX(0x180)
+#define DM816_TIMER6_CLKCTRL DM816_CLKCTRL_INDEX(0x184)
+#define DM816_TIMER7_CLKCTRL DM816_CLKCTRL_INDEX(0x188)
+#define DM816_WD_TIMER_CLKCTRL DM816_CLKCTRL_INDEX(0x18c)
+#define DM816_MCSPI1_CLKCTRL DM816_CLKCTRL_INDEX(0x190)
+#define DM816_MAILBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x194)
+#define DM816_SPINBOX_CLKCTRL DM816_CLKCTRL_INDEX(0x198)
+#define DM816_MMC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1b0)
+#define DM816_GPMC_CLKCTRL DM816_CLKCTRL_INDEX(0x1d0)
+#define DM816_DAVINCI_MDIO_CLKCTRL DM816_CLKCTRL_INDEX(0x1d4)
+#define DM816_EMAC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1d8)
+#define DM816_MPU_CLKCTRL DM816_CLKCTRL_INDEX(0x1dc)
+#define DM816_RTC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f0)
+#define DM816_TPCC_CLKCTRL DM816_CLKCTRL_INDEX(0x1f4)
+#define DM816_TPTC0_CLKCTRL DM816_CLKCTRL_INDEX(0x1f8)
+#define DM816_TPTC1_CLKCTRL DM816_CLKCTRL_INDEX(0x1fc)
+#define DM816_TPTC2_CLKCTRL DM816_CLKCTRL_INDEX(0x200)
+#define DM816_TPTC3_CLKCTRL DM816_CLKCTRL_INDEX(0x204)
+
+#endif
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h
new file mode 100644
index 0000000..5e1061b
--- /dev/null
+++ b/include/dt-bindings/clock/dra7.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_DRA7_H
+#define __DT_BINDINGS_CLK_DRA7_H
+
+#define DRA7_CLKCTRL_OFFSET 0x20
+#define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET)
+
+/* mpu clocks */
+#define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+
+/* ipu clocks */
+#define DRA7_IPU_CLKCTRL_OFFSET 0x40
+#define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
+#define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
+#define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
+#define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
+#define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
+#define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
+#define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78)
+#define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80)
+
+/* rtc clocks */
+#define DRA7_RTC_CLKCTRL_OFFSET 0x40
+#define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET)
+#define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44)
+
+/* coreaon clocks */
+#define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
+
+/* l3main1 clocks */
+#define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
+#define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
+#define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
+
+/* dma clocks */
+#define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+
+/* emif clocks */
+#define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+
+/* atl clocks */
+#define DRA7_ATL_CLKCTRL_OFFSET 0x0
+#define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
+#define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0)
+
+/* l4cfg clocks */
+#define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58)
+#define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60)
+#define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68)
+#define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70)
+#define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78)
+#define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90)
+#define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98)
+#define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
+
+/* l3instr clocks */
+#define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+
+/* dss clocks */
+#define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+
+/* l3init clocks */
+#define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28)
+#define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
+#define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0)
+#define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8)
+#define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0)
+#define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0)
+#define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8)
+#define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
+
+/* l4per clocks */
+#define DRA7_L4PER_CLKCTRL_OFFSET 0x0
+#define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
+#define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc)
+#define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14)
+#define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28)
+#define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30)
+#define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38)
+#define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40)
+#define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48)
+#define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50)
+#define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58)
+#define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60)
+#define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68)
+#define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70)
+#define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78)
+#define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80)
+#define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88)
+#define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90)
+#define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98)
+#define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
+#define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
+#define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
+#define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
+#define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0)
+#define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4)
+#define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8)
+#define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0)
+#define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8)
+#define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0)
+#define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8)
+#define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100)
+#define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108)
+#define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110)
+#define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118)
+#define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
+#define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
+#define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130)
+#define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138)
+#define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140)
+#define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148)
+#define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150)
+#define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158)
+#define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160)
+#define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168)
+#define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170)
+#define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178)
+#define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190)
+#define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198)
+#define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0)
+#define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8)
+#define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0)
+#define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0)
+#define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8)
+#define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0)
+#define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0)
+#define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8)
+#define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0)
+#define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204)
+#define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208)
+
+/* wkupaon clocks */
+#define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
+#define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30)
+#define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38)
+#define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
+#define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
+#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
+#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
+#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
+
+#endif
diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h
index adb768d..75d583e 100644
--- a/include/dt-bindings/clock/hi3660-clock.h
+++ b/include/dt-bindings/clock/hi3660-clock.h
@@ -208,4 +208,11 @@
#define HI3660_CLK_I2C6_IOMCU 3
#define HI3660_CLK_IOMCU_PERI0 4
+/* clk in stub clock */
+#define HI3660_CLK_STUB_CLUSTER0 0
+#define HI3660_CLK_STUB_CLUSTER1 1
+#define HI3660_CLK_STUB_GPU 2
+#define HI3660_CLK_STUB_DDR 3
+#define HI3660_CLK_STUB_NUM 4
+
#endif /* __DTS_HI3660_CLOCK_H */
diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h
new file mode 100644
index 0000000..f51821a
--- /dev/null
+++ b/include/dt-bindings/clock/omap5.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2017 Texas Instruments, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_CLK_OMAP5_H
+#define __DT_BINDINGS_CLK_OMAP5_H
+
+#define OMAP5_CLKCTRL_OFFSET 0x20
+#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
+
+/* mpu clocks */
+#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* dsp clocks */
+#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* abe clocks */
+#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
+#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
+#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
+#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
+
+/* l3main1 clocks */
+#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* l3main2 clocks */
+#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* ipu clocks */
+#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* dma clocks */
+#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* emif clocks */
+#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+
+/* l4cfg clocks */
+#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+
+/* l3instr clocks */
+#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+
+/* l4per clocks */
+#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
+#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
+#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
+#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
+#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
+#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
+#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
+#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
+#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
+#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
+#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
+#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
+#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
+#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
+#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
+#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
+#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
+#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
+#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
+#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
+#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
+#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
+#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
+#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
+#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
+#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
+
+/* dss clocks */
+#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+
+/* l3init clocks */
+#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
+#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
+#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
+#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
+#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
+#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
+#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
+
+/* wkupaon clocks */
+#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
+#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
+#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
+#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
+#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
+#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
index 370c83c..238f872 100644
--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
@@ -58,6 +58,186 @@
#define GCC_QPIC_AHB_CLK 41
#define GCC_QPIC_CLK 42
#define PCNOC_BFDCD_CLK_SRC 43
+#define GPLL2_MAIN 44
+#define GPLL2 45
+#define GPLL4_MAIN 46
+#define GPLL4 47
+#define GPLL6_MAIN 48
+#define GPLL6 49
+#define UBI32_PLL_MAIN 50
+#define UBI32_PLL 51
+#define NSS_CRYPTO_PLL_MAIN 52
+#define NSS_CRYPTO_PLL 53
+#define PCIE0_AXI_CLK_SRC 54
+#define PCIE0_AUX_CLK_SRC 55
+#define PCIE0_PIPE_CLK_SRC 56
+#define PCIE1_AXI_CLK_SRC 57
+#define PCIE1_AUX_CLK_SRC 58
+#define PCIE1_PIPE_CLK_SRC 59
+#define SDCC1_APPS_CLK_SRC 60
+#define SDCC1_ICE_CORE_CLK_SRC 61
+#define SDCC2_APPS_CLK_SRC 62
+#define USB0_MASTER_CLK_SRC 63
+#define USB0_AUX_CLK_SRC 64
+#define USB0_MOCK_UTMI_CLK_SRC 65
+#define USB0_PIPE_CLK_SRC 66
+#define USB1_MASTER_CLK_SRC 67
+#define USB1_AUX_CLK_SRC 68
+#define USB1_MOCK_UTMI_CLK_SRC 69
+#define USB1_PIPE_CLK_SRC 70
+#define GCC_XO_CLK_SRC 71
+#define SYSTEM_NOC_BFDCD_CLK_SRC 72
+#define NSS_CE_CLK_SRC 73
+#define NSS_NOC_BFDCD_CLK_SRC 74
+#define NSS_CRYPTO_CLK_SRC 75
+#define NSS_UBI0_CLK_SRC 76
+#define NSS_UBI0_DIV_CLK_SRC 77
+#define NSS_UBI1_CLK_SRC 78
+#define NSS_UBI1_DIV_CLK_SRC 79
+#define UBI_MPT_CLK_SRC 80
+#define NSS_IMEM_CLK_SRC 81
+#define NSS_PPE_CLK_SRC 82
+#define NSS_PORT1_RX_CLK_SRC 83
+#define NSS_PORT1_RX_DIV_CLK_SRC 84
+#define NSS_PORT1_TX_CLK_SRC 85
+#define NSS_PORT1_TX_DIV_CLK_SRC 86
+#define NSS_PORT2_RX_CLK_SRC 87
+#define NSS_PORT2_RX_DIV_CLK_SRC 88
+#define NSS_PORT2_TX_CLK_SRC 89
+#define NSS_PORT2_TX_DIV_CLK_SRC 90
+#define NSS_PORT3_RX_CLK_SRC 91
+#define NSS_PORT3_RX_DIV_CLK_SRC 92
+#define NSS_PORT3_TX_CLK_SRC 93
+#define NSS_PORT3_TX_DIV_CLK_SRC 94
+#define NSS_PORT4_RX_CLK_SRC 95
+#define NSS_PORT4_RX_DIV_CLK_SRC 96
+#define NSS_PORT4_TX_CLK_SRC 97
+#define NSS_PORT4_TX_DIV_CLK_SRC 98
+#define NSS_PORT5_RX_CLK_SRC 99
+#define NSS_PORT5_RX_DIV_CLK_SRC 100
+#define NSS_PORT5_TX_CLK_SRC 101
+#define NSS_PORT5_TX_DIV_CLK_SRC 102
+#define NSS_PORT6_RX_CLK_SRC 103
+#define NSS_PORT6_RX_DIV_CLK_SRC 104
+#define NSS_PORT6_TX_CLK_SRC 105
+#define NSS_PORT6_TX_DIV_CLK_SRC 106
+#define CRYPTO_CLK_SRC 107
+#define GP1_CLK_SRC 108
+#define GP2_CLK_SRC 109
+#define GP3_CLK_SRC 110
+#define GCC_PCIE0_AHB_CLK 111
+#define GCC_PCIE0_AUX_CLK 112
+#define GCC_PCIE0_AXI_M_CLK 113
+#define GCC_PCIE0_AXI_S_CLK 114
+#define GCC_PCIE0_PIPE_CLK 115
+#define GCC_SYS_NOC_PCIE0_AXI_CLK 116
+#define GCC_PCIE1_AHB_CLK 117
+#define GCC_PCIE1_AUX_CLK 118
+#define GCC_PCIE1_AXI_M_CLK 119
+#define GCC_PCIE1_AXI_S_CLK 120
+#define GCC_PCIE1_PIPE_CLK 121
+#define GCC_SYS_NOC_PCIE1_AXI_CLK 122
+#define GCC_USB0_AUX_CLK 123
+#define GCC_SYS_NOC_USB0_AXI_CLK 124
+#define GCC_USB0_MASTER_CLK 125
+#define GCC_USB0_MOCK_UTMI_CLK 126
+#define GCC_USB0_PHY_CFG_AHB_CLK 127
+#define GCC_USB0_PIPE_CLK 128
+#define GCC_USB0_SLEEP_CLK 129
+#define GCC_USB1_AUX_CLK 130
+#define GCC_SYS_NOC_USB1_AXI_CLK 131
+#define GCC_USB1_MASTER_CLK 132
+#define GCC_USB1_MOCK_UTMI_CLK 133
+#define GCC_USB1_PHY_CFG_AHB_CLK 134
+#define GCC_USB1_PIPE_CLK 135
+#define GCC_USB1_SLEEP_CLK 136
+#define GCC_SDCC1_AHB_CLK 137
+#define GCC_SDCC1_APPS_CLK 138
+#define GCC_SDCC1_ICE_CORE_CLK 139
+#define GCC_SDCC2_AHB_CLK 140
+#define GCC_SDCC2_APPS_CLK 141
+#define GCC_MEM_NOC_NSS_AXI_CLK 142
+#define GCC_NSS_CE_APB_CLK 143
+#define GCC_NSS_CE_AXI_CLK 144
+#define GCC_NSS_CFG_CLK 145
+#define GCC_NSS_CRYPTO_CLK 146
+#define GCC_NSS_CSR_CLK 147
+#define GCC_NSS_EDMA_CFG_CLK 148
+#define GCC_NSS_EDMA_CLK 149
+#define GCC_NSS_IMEM_CLK 150
+#define GCC_NSS_NOC_CLK 151
+#define GCC_NSS_PPE_BTQ_CLK 152
+#define GCC_NSS_PPE_CFG_CLK 153
+#define GCC_NSS_PPE_CLK 154
+#define GCC_NSS_PPE_IPE_CLK 155
+#define GCC_NSS_PTP_REF_CLK 156
+#define GCC_NSSNOC_CE_APB_CLK 157
+#define GCC_NSSNOC_CE_AXI_CLK 158
+#define GCC_NSSNOC_CRYPTO_CLK 159
+#define GCC_NSSNOC_PPE_CFG_CLK 160
+#define GCC_NSSNOC_PPE_CLK 161
+#define GCC_NSSNOC_QOSGEN_REF_CLK 162
+#define GCC_NSSNOC_SNOC_CLK 163
+#define GCC_NSSNOC_TIMEOUT_REF_CLK 164
+#define GCC_NSSNOC_UBI0_AHB_CLK 165
+#define GCC_NSSNOC_UBI1_AHB_CLK 166
+#define GCC_UBI0_AHB_CLK 167
+#define GCC_UBI0_AXI_CLK 168
+#define GCC_UBI0_NC_AXI_CLK 169
+#define GCC_UBI0_CORE_CLK 170
+#define GCC_UBI0_MPT_CLK 171
+#define GCC_UBI1_AHB_CLK 172
+#define GCC_UBI1_AXI_CLK 173
+#define GCC_UBI1_NC_AXI_CLK 174
+#define GCC_UBI1_CORE_CLK 175
+#define GCC_UBI1_MPT_CLK 176
+#define GCC_CMN_12GPLL_AHB_CLK 177
+#define GCC_CMN_12GPLL_SYS_CLK 178
+#define GCC_MDIO_AHB_CLK 179
+#define GCC_UNIPHY0_AHB_CLK 180
+#define GCC_UNIPHY0_SYS_CLK 181
+#define GCC_UNIPHY1_AHB_CLK 182
+#define GCC_UNIPHY1_SYS_CLK 183
+#define GCC_UNIPHY2_AHB_CLK 184
+#define GCC_UNIPHY2_SYS_CLK 185
+#define GCC_NSS_PORT1_RX_CLK 186
+#define GCC_NSS_PORT1_TX_CLK 187
+#define GCC_NSS_PORT2_RX_CLK 188
+#define GCC_NSS_PORT2_TX_CLK 189
+#define GCC_NSS_PORT3_RX_CLK 190
+#define GCC_NSS_PORT3_TX_CLK 191
+#define GCC_NSS_PORT4_RX_CLK 192
+#define GCC_NSS_PORT4_TX_CLK 193
+#define GCC_NSS_PORT5_RX_CLK 194
+#define GCC_NSS_PORT5_TX_CLK 195
+#define GCC_NSS_PORT6_RX_CLK 196
+#define GCC_NSS_PORT6_TX_CLK 197
+#define GCC_PORT1_MAC_CLK 198
+#define GCC_PORT2_MAC_CLK 199
+#define GCC_PORT3_MAC_CLK 200
+#define GCC_PORT4_MAC_CLK 201
+#define GCC_PORT5_MAC_CLK 202
+#define GCC_PORT6_MAC_CLK 203
+#define GCC_UNIPHY0_PORT1_RX_CLK 204
+#define GCC_UNIPHY0_PORT1_TX_CLK 205
+#define GCC_UNIPHY0_PORT2_RX_CLK 206
+#define GCC_UNIPHY0_PORT2_TX_CLK 207
+#define GCC_UNIPHY0_PORT3_RX_CLK 208
+#define GCC_UNIPHY0_PORT3_TX_CLK 209
+#define GCC_UNIPHY0_PORT4_RX_CLK 210
+#define GCC_UNIPHY0_PORT4_TX_CLK 211
+#define GCC_UNIPHY0_PORT5_RX_CLK 212
+#define GCC_UNIPHY0_PORT5_TX_CLK 213
+#define GCC_UNIPHY1_PORT5_RX_CLK 214
+#define GCC_UNIPHY1_PORT5_TX_CLK 215
+#define GCC_UNIPHY2_PORT6_RX_CLK 216
+#define GCC_UNIPHY2_PORT6_TX_CLK 217
+#define GCC_CRYPTO_AHB_CLK 218
+#define GCC_CRYPTO_AXI_CLK 219
+#define GCC_CRYPTO_CLK 220
+#define GCC_GP1_CLK 221
+#define GCC_GP2_CLK 222
+#define GCC_GP3_CLK 223
#define GCC_BLSP1_BCR 0
#define GCC_BLSP1_QUP1_BCR 1
@@ -148,5 +328,47 @@
#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 86
#define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR 87
#define GCC_SMMU_CATS_BCR 88
+#define GCC_UBI0_AXI_ARES 89
+#define GCC_UBI0_AHB_ARES 90
+#define GCC_UBI0_NC_AXI_ARES 91
+#define GCC_UBI0_DBG_ARES 92
+#define GCC_UBI0_CORE_CLAMP_ENABLE 93
+#define GCC_UBI0_CLKRST_CLAMP_ENABLE 94
+#define GCC_UBI1_AXI_ARES 95
+#define GCC_UBI1_AHB_ARES 96
+#define GCC_UBI1_NC_AXI_ARES 97
+#define GCC_UBI1_DBG_ARES 98
+#define GCC_UBI1_CORE_CLAMP_ENABLE 99
+#define GCC_UBI1_CLKRST_CLAMP_ENABLE 100
+#define GCC_NSS_CFG_ARES 101
+#define GCC_NSS_IMEM_ARES 102
+#define GCC_NSS_NOC_ARES 103
+#define GCC_NSS_CRYPTO_ARES 104
+#define GCC_NSS_CSR_ARES 105
+#define GCC_NSS_CE_APB_ARES 106
+#define GCC_NSS_CE_AXI_ARES 107
+#define GCC_NSSNOC_CE_APB_ARES 108
+#define GCC_NSSNOC_CE_AXI_ARES 109
+#define GCC_NSSNOC_UBI0_AHB_ARES 110
+#define GCC_NSSNOC_UBI1_AHB_ARES 111
+#define GCC_NSSNOC_SNOC_ARES 112
+#define GCC_NSSNOC_CRYPTO_ARES 113
+#define GCC_NSSNOC_ATB_ARES 114
+#define GCC_NSSNOC_QOSGEN_REF_ARES 115
+#define GCC_NSSNOC_TIMEOUT_REF_ARES 116
+#define GCC_PCIE0_PIPE_ARES 117
+#define GCC_PCIE0_SLEEP_ARES 118
+#define GCC_PCIE0_CORE_STICKY_ARES 119
+#define GCC_PCIE0_AXI_MASTER_ARES 120
+#define GCC_PCIE0_AXI_SLAVE_ARES 121
+#define GCC_PCIE0_AHB_ARES 122
+#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 123
+#define GCC_PCIE1_PIPE_ARES 124
+#define GCC_PCIE1_SLEEP_ARES 125
+#define GCC_PCIE1_CORE_STICKY_ARES 126
+#define GCC_PCIE1_AXI_MASTER_ARES 127
+#define GCC_PCIE1_AXI_SLAVE_ARES 128
+#define GCC_PCIE1_AHB_ARES 129
+#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
#endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 26ea037..411db24 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -744,6 +744,7 @@ unsigned long clk_hw_get_rate(const struct clk_hw *hw);
unsigned long __clk_get_flags(struct clk *clk);
unsigned long clk_hw_get_flags(const struct clk_hw *hw);
bool clk_hw_is_prepared(const struct clk_hw *hw);
+bool clk_hw_rate_is_protected(const struct clk_hw *hw);
bool clk_hw_is_enabled(const struct clk_hw *hw);
bool __clk_is_enabled(struct clk *clk);
struct clk *__clk_lookup(const char *name);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 12c96d9..4c4ef9f 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -331,6 +331,38 @@ struct clk *devm_clk_get(struct device *dev, const char *id);
*/
struct clk *devm_get_clk_from_child(struct device *dev,
struct device_node *np, const char *con_id);
+/**
+ * clk_rate_exclusive_get - get exclusivity over the rate control of a
+ * producer
+ * @clk: clock source
+ *
+ * This function allows drivers to get exclusive control over the rate of a
+ * provider. It prevents any other consumer to execute, even indirectly,
+ * opereation which could alter the rate of the provider or cause glitches
+ *
+ * If exlusivity is claimed more than once on clock, even by the same driver,
+ * the rate effectively gets locked as exclusivity can't be preempted.
+ *
+ * Must not be called from within atomic context.
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_rate_exclusive_get(struct clk *clk);
+
+/**
+ * clk_rate_exclusive_put - release exclusivity over the rate control of a
+ * producer
+ * @clk: clock source
+ *
+ * This function allows drivers to release the exclusivity it previously got
+ * from clk_rate_exclusive_get()
+ *
+ * The caller must balance the number of clk_rate_exclusive_get() and
+ * clk_rate_exclusive_put() calls.
+ *
+ * Must not be called from within atomic context.
+ */
+void clk_rate_exclusive_put(struct clk *clk);
/**
* clk_enable - inform the system when the clock source should be running.
@@ -473,6 +505,23 @@ long clk_round_rate(struct clk *clk, unsigned long rate);
int clk_set_rate(struct clk *clk, unsigned long rate);
/**
+ * clk_set_rate_exclusive- set the clock rate and claim exclusivity over
+ * clock source
+ * @clk: clock source
+ * @rate: desired clock rate in Hz
+ *
+ * This helper function allows drivers to atomically set the rate of a producer
+ * and claim exclusivity over the rate control of the producer.
+ *
+ * It is essentially a combination of clk_set_rate() and
+ * clk_rate_exclusite_get(). Caller must balance this call with a call to
+ * clk_rate_exclusive_put()
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate_exclusive(struct clk *clk, unsigned long rate);
+
+/**
* clk_has_parent - check if a clock is a possible parent for another
* @clk: clock source
* @parent: parent clock source
@@ -583,6 +632,14 @@ static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {}
static inline void devm_clk_put(struct device *dev, struct clk *clk) {}
+
+static inline int clk_rate_exclusive_get(struct clk *clk)
+{
+ return 0;
+}
+
+static inline void clk_rate_exclusive_put(struct clk *clk) {}
+
static inline int clk_enable(struct clk *clk)
{
return 0;
@@ -609,6 +666,11 @@ static inline int clk_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
+static inline int clk_set_rate_exclusive(struct clk *clk, unsigned long rate)
+{
+ return 0;
+}
+
static inline long clk_round_rate(struct clk *clk, unsigned long rate)
{
return 0;
diff --git a/include/trace/events/clk.h b/include/trace/events/clk.h
index 7586072..2cd4493 100644
--- a/include/trace/events/clk.h
+++ b/include/trace/events/clk.h
@@ -134,12 +134,12 @@ DECLARE_EVENT_CLASS(clk_parent,
TP_STRUCT__entry(
__string( name, core->name )
- __string( pname, parent->name )
+ __string( pname, parent ? parent->name : "none" )
),
TP_fast_assign(
__assign_str(name, core->name);
- __assign_str(pname, parent->name);
+ __assign_str(pname, parent ? parent->name : "none");
),
TP_printk("%s %s", __get_str(name), __get_str(pname))