| commit | 7f170499f734c417290518aa50cac11953bf8161 | [log] [tgz] |
|---|---|---|
| author | Philip Elcan <pelcan@codeaurora.org> | Tue Mar 27 21:55:32 2018 -0400 |
| committer | Will Deacon <will.deacon@arm.com> | Wed Mar 28 15:20:17 2018 +0100 |
| tree | 57430fc906fc301e499c2beadb8df75b1c6f50be | |
| parent | 2a58fca9a7b4a3953c3e983ef80e36df85293a7c [diff] |
arm64: tlbflush: avoid writing RES0 bits Several of the bits of the TLBI register operand are RES0 per the ARM ARM, so TLBI operations should avoid writing non-zero values to these bits. This patch adds a macro __TLBI_VADDR(addr, asid) that creates the operand register in the correct format and honors the RES0 bits. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Philip Elcan <pelcan@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>