tree c53691a74ed5d06c6fd294f96441b481c581cafb
parent 7ce7d89f48834cefece7804d38fc5d85382edf77
author Sudeep Holla <sudeep.holla@arm.com> 1481639093 +0000
committer Sudeep Holla <sudeep.holla@arm.com> 1483111884 +0000

arm64: dts: vexpress: Support GICC_DIR operations

The GICv2 CPU interface registers span across 8K, not 4K as indicated in
the DT.  Only the GICC_DIR register is located after the initial 4K
boundary, leaving a functional system but without support for separately
EOI'ing and deactivating interrupts.

After this change the system supports split priority drop and interrupt
deactivation. This patch is based on similar one from Christoffer Dall:
commit 368400e242dc ("ARM: dts: vexpress: Support GICC_DIR operations")

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>