tree 37409358acf86db952e0216fa528d289eef4fc4d
parent 43c734be5571a4daad9f0a3e0b3229a1c0049917
author Catalin Marinas <catalin.marinas@arm.com> 1313402681 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1313405939 +0100

ARM: 7015/1: ARM errata: Possible cache data corruption with hit-under-miss enabled

This patch is a workaround for the 364296 ARM1136 r0p2 erratum (possible
cache data corruption with hit-under-miss enabled). It sets the
undocumented bit 31 in the auxiliary control register and the FI bit in
the control register, thus disabling hit-under-miss without putting the
processor into full low interrupt latency mode.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>