commit | 13136a47a061c01c91df78b37f7708dd5ce7035f | [log] [tgz] |
---|---|---|
author | Aapo Vienamo <avienamo@nvidia.com> | Fri Aug 10 21:08:07 2018 +0300 |
committer | Thierry Reding <treding@nvidia.com> | Mon Aug 27 12:25:17 2018 +0200 |
tree | 231b0f8fefa0be14b109b2502011adea6c77bd87 | |
parent | 1dc6bd5e39a29453bdcc17348dd2a89f1aa4004e [diff] |
soc/tegra: pmc: Fix pad voltage configuration for Tegra186 Implement support for the PMC_IMPL_E_33V_PWR register which replaces PMC_PWR_DET register interface of the SoC generations preceding Tegra186. Also add the voltage bit offsets to the tegra186_io_pads[] table and the AO_HV pad. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>