commit | 11d764079c9f25d1da8e10906d54da7fefec5844 | [log] [tgz] |
---|---|---|
author | Marc Zyngier <marc.zyngier@arm.com> | Sun Dec 03 17:50:00 2017 +0000 |
committer | Marc Zyngier <marc.zyngier@arm.com> | Mon Mar 19 13:05:13 2018 +0000 |
tree | 02f756085f8258d087dc0ae1c4196933dc7e2f8a | |
parent | 9f2efa320d395050abd0f39842843bb460736515 [diff] |
arm64: insn: Allow ADD/SUB (immediate) with LSL #12 The encoder for ADD/SUB (immediate) can only cope with 12bit immediates, while there is an encoding for a 12bit immediate shifted by 12 bits to the left. Let's fix this small oversight by allowing the LSL_12 bit to be set. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>