| commit | 103afc8e9e8c4eff96052b311d19f7c32b653ebb | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Thu Mar 19 13:27:36 2020 +0100 |
| committer | Linus Walleij <linus.walleij@linaro.org> | Fri Mar 27 11:44:59 2020 +0100 |
| tree | b201003c0a231cff3afa2b7a14fc93bdfcd965c6 | |
| parent | f67499f8ea7c15818d3375d718bd6cde4ae3d4f5 [diff] |
pinctrl: tegra: Renumber the GG.0 and GG.1 pins There is no need to define these at a specific offset since they are the only pins defined for this SoC generation. Begin numbering them at 0. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com Tested-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>