| commit | 0fa400cb8a90753044bbcb5810fa1a59d96d5ea1 | [log] [tgz] |
|---|---|---|
| author | Vineet Gupta <vgupta@synopsys.com> | Tue Aug 22 14:37:22 2017 -0700 |
| committer | Vineet Gupta <vgupta@synopsys.com> | Fri Sep 01 11:26:26 2017 -0700 |
| tree | 76080e940d4b0fdde189ea918e80295a10f6e8c5 | |
| parent | f6a09bace0bb9587985b48ed652f2b292f8de0de [diff] |
ARC: [plat-axs103] refactor the DT fudging code with clk frequency setting code gone by prev commits, we can elide the unconditonal DT parsing to the specific case of quad core config where we possibly need to fudge the DT value. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>