| commit | 0d18f2dfead8dd63bf1186c9ef38528d6a615a55 | [log] [tgz] |
|---|---|---|
| author | Kan Liang <kan.liang@linux.intel.com> | Mon Apr 12 07:30:48 2021 -0700 |
| committer | Peter Zijlstra <peterz@infradead.org> | Mon Apr 19 20:03:25 2021 +0200 |
| tree | 5dba9ccd7d54ca4a549bc2cb0180dec52e5c0fa9 | |
| parent | eaacf07d1116f6bf3b93b265515fccf2301097f2 [diff] |
perf/x86: Hybrid PMU support for hardware cache event The hardware cache events are different among hybrid PMUs. Each hybrid PMU should have its own hw cache event table. Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/1618237865-33448-9-git-send-email-kan.liang@linux.intel.com