| commit | 0d0d498265e7cb3329d2a7185b1d7cfb3be95d65 | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Mon Dec 09 13:00:04 2019 +0100 |
| committer | Ben Skeggs <bskeggs@redhat.com> | Wed Jan 15 10:49:59 2020 +1000 |
| tree | 6c7b57f1c2c9e2424fe05157686d58c5917fb573 | |
| parent | 6992ceb8c0f6f8e2f4374a1ab4dd84cd76cc4b64 [diff] |
drm/nouveau/ltc/gp10b: Add custom L2 cache implementation There are extra registers that need to be programmed to make the level 2 cache work on GP10B, such as the stream ID register that is used when an SMMU is used to translate memory addresses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>