| commit | 049d919168458ac54e7fad27cd156a958b042d2f | [log] [tgz] |
|---|---|---|
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | Tue Feb 25 20:56:43 2020 +0800 |
| committer | Will Deacon <will@kernel.org> | Mon Mar 02 12:07:19 2020 +0000 |
| tree | 7a1fa34cf4825d70c3bbdef0c9b9d6760f0abe75 | |
| parent | dcde237319e626d1ec3c9d8b7613032f0fd4663a [diff] |
drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition When disabling a counter from ddr_perf_event_stop(), the counter value is reset to 0 at the same time. Preserve the counter value by performing a read-modify-write of the PMU register and clearing only the enable bit. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: Will Deacon <will@kernel.org>