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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / c72c3b597a79508a54857b34b5aa55b49db889b4 / arch / riscv / include / asm / csr.h
  1. a2da5b1 RISC-V: Remove N-extension related defines by Anup Patel · 4 years, 9 months ago
  2. c68a903 riscv: set pmp configuration if kernel is running in M-mode by Greentime Hu · 5 years ago
  3. 2f3035d riscv: prefix IRQ_ macro names with an RV_ namespace by Paul Walmsley · 5 years ago
  4. 9e80635 riscv: clear the instruction cache and all registers when booting by Christoph Hellwig · 5 years ago
  5. accb9db riscv: read the hart ID from mhartid on boot by Damien Le Moal · 5 years ago
  6. a4c3733 riscv: abstract out CSR names for supervisor vs machine mode by Christoph Hellwig · 5 years ago
  7. 50acfb2 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286 by Thomas Gleixner · 6 years ago
  8. a3182c9 RISC-V: Access CSRs using CSR numbers by Anup Patel · 6 years ago
  9. 6dcaf00 RISC-V: Add interrupt related SCAUSE defines in asm/csr.h by Anup Patel · 6 years ago
  10. 196a14d RISC-V: Use tabs to align macro values in asm/csr.h by Anup Patel · 6 years ago
  11. bec2e6a RISC-V: add a definition for the SIE SEIE bit by Christoph Hellwig · 6 years ago
  12. 7549cdf riscv: rename sptbr to satp by Christoph Hellwig · 7 years ago
  13. 1125203 riscv: rename SR_* constants to match the spec by Christoph Hellwig · 7 years ago
  14. 5d8544e RISC-V: Generic library routines and assembly by Palmer Dabbelt · 8 years ago