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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 7993b3ebec979b23c2d7425959c9d232c452498b / Documentation / devicetree / bindings / clock / sunxi.txt
  1. ec80749 clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCs by Hans de Goede · 10 years ago
  2. 9f24309 clk: sunxi: Add muxable ahb factors clock for sun5i and sun7i by Chen-Yu Tsai · 10 years ago
  3. 71f32f5 clk: sunxi: Add support for sun9i A80 USB clocks and resets by Chen-Yu Tsai · 10 years ago
  4. 7a6fca8 clk: sunxi: Add driver for A80 MMC config clocks/resets by Chen-Yu Tsai · 10 years ago
  5. 61af4d8 clk: sunxi: Add mod0 and mmc module clock support for A80 by Chen-Yu Tsai · 10 years ago
  6. 6b0b8cc clk: sunxi: Rework MMC phase clocks by Maxime Ripard · 10 years ago
  7. 7954dfa clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider by Chen-Yu Tsai · 10 years ago
  8. 95e94c1 clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output by Chen-Yu Tsai · 10 years ago
  9. eaa2e98 clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driver by Chen-Yu Tsai · 10 years ago
  10. 93746e7 clk: sunxi: unify APB1 clock by Emilio López · 10 years ago
  11. 0b0f080 clk: sunxi: Add support for bus clock gates on Allwinner A80 SoC by Chen-Yu Tsai · 10 years ago
  12. 3b2bd70 clk: sunxi: Add support for A80 basic bus clocks by Chen-Yu Tsai · 10 years ago
  13. 9c8176b clk: sunxi: Add sun8i MBUS clock support by Chen-Yu Tsai · 10 years ago
  14. 37e1041 clk: sunxi: mod0: Introduce MMC proper phase handling by Maxime Ripard · 11 years ago
  15. 03e29bb clk: sunxi: Introduce mbus compatible by Maxime Ripard · 11 years ago
  16. 6c1d66f clk: sunxi: sun6i-a31-apb0-gates: Add A23 APB0 support by Chen-Yu Tsai · 11 years ago
  17. 57a1fbf2 clk: sunxi: Add A23 APB0 divider clock support by Chen-Yu Tsai · 11 years ago
  18. 515c1a4 clk: sunxi: Add A23 clocks support by Chen-Yu Tsai · 11 years ago
  19. 5c89a8b clk: sunxi: document PRCM clock compatible strings by Boris BREZILLON · 11 years ago
  20. 6d1d14d clk: sunxi: document new A31 USB clock compatible by Emilio López · 11 years ago
  21. fd1b22f clk: sunxi: Add new clock compatibles by Maxime Ripard · 11 years ago
  22. e4c6d6c clk: sunxi: Add Allwinner A20/A31 GMAC clock unit by Chen-Yu Tsai · 11 years ago
  23. 92ef67c clk: sunxi: Add support for PLL6 on the A31 by Maxime Ripard · 11 years ago
  24. 5abdbf2 clk: sunxi: Add USB clock register defintions by Roman Byshko · 11 years ago
  25. 373d4e6 clk: sunxi: update clock-output-names dt binding documentation by Chen-Yu Tsai · 11 years ago
  26. 6f86341 clk: sunxi: Allwinner A20 output clock support by Chen-Yu Tsai · 11 years ago
  27. 7551769 clk: sunxi: mod0 support by Emilio López · 11 years ago
  28. d584c13 clk: sunxi: add PLL5 and PLL6 support by Emilio López · 11 years ago
  29. d838ff3 clk: sunxi: add gating support to PLL1 by Emilio López · 11 years ago
  30. fc42ef5 Documentation: dt: Remove clock gates IDs list for Allwinner SoCs by Maxime Ripard · 11 years ago
  31. 1fb2e4a clk: sunxi: Add Allwinner A20 gates by Maxime Ripard · 11 years ago
  32. 6a721db clk: sunxi: Add A31 clocks support by Maxime Ripard · 11 years ago
  33. 2371dd8 clk: sunxi: Add A10s gates by Maxime Ripard · 12 years ago
  34. 4f985b4 clk: sun5i: Add compatibles for Allwinner A13 by Maxime Ripard · 12 years ago
  35. 13569a7 clk: sunxi: Add support for AXI, AHB, APB0 and APB1 gates by Emilio López · 12 years ago
  36. e327699 clk: sunxi: rename compatible strings by Emilio López · 12 years ago
  37. e874a66 clk: arm: sunxi: Add a new clock driver for sunxi SOCs by Emilio López · 12 years ago