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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 6e5a663d8e5c6a39ba0a98058ee94796e835fb98 / drivers / fpga / zynq-fpga.c
  1. d20c0da fpga: Remove dev_err() usage after platform_get_irq() by Stephen Boyd · 5 years ago
  2. 8e8e69d treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285 by Thomas Gleixner · 6 years ago
  3. 9e9a615 zynq-fpga: Only route PR via PCAP when required by Mike Looijmans · 6 years ago
  4. 084181f fpga: mgr: add devm_fpga_mgr_create by Alan Tull · 6 years ago
  5. 7085e2a fpga: manager: change api, don't use drvdata by Alan Tull · 7 years ago
  6. 7f33bbc fpga: zynq: Add support for encrypted bitstreams by Moritz Fischer · 8 years ago
  7. 425902f fpga zynq: Use the scatterlist interface by Jason Gunthorpe · 8 years ago
  8. b496df8 fpga zynq: Check the bitstream for validity by Jason Gunthorpe · 8 years ago
  9. 6b45e0f fpga zynq: Check for errors after completing DMA by Jason Gunthorpe · 8 years ago
  10. 340c0c5 fpga zynq: Fix incorrect ISR state on bootup by Jason Gunthorpe · 8 years ago
  11. 80baf64 fpga zynq: Remove priv->dev by Jason Gunthorpe · 8 years ago
  12. 1930c28 fpga zynq: Add missing \n to messages by Jason Gunthorpe · 8 years ago
  13. 1df2865 fpga-mgr: add fpga image information struct by Alan Tull · 8 years ago
  14. 28f98a1 fpga: zynq-fpga: Fix issue with drvdata being overwritten. by Moritz Fischer · 9 years ago
  15. 4d10eaf fpga: zynq-fpga: Change fw format to handle bin instead of bit. by Moritz Fischer · 9 years ago
  16. 6376931 fpga: zynq-fpga: Fix unbalanced clock handling by Moritz Fischer · 9 years ago
  17. 3778470 fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000 by Moritz Fischer · 9 years ago