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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 557c7ffa2f283166fa863aaa415757f5f485aa62 / drivers / clk / clk-versaclock5.c
  1. c942fdd treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157 by Thomas Gleixner · 6 years ago
  2. 2137a10 clk: vc5: Abort clock configuration without upstream clock by Marek Vasut · 6 years ago
  3. 8cbdc1f clk: vc5: Add suspend/resume support by Marek Vasut · 6 years ago
  4. b191155 clk: vc5: Add support for IDT VersaClock 5P49V5925 by Vladimir Barinov · 7 years ago
  5. dbf6b16 clk: vc5: Add support for IDT VersaClock 5P49V6901 by Marek Vasut · 7 years ago
  6. 8c1ebe9 clk: vc5: Add support for the input frequency doubler by Marek Vasut · 7 years ago
  7. 55997db clk: vc5: Split clock input mux and predivider by Marek Vasut · 7 years ago
  8. 718f469 clk: vc5: Configure the output buffer input mux on prepare by Marek Vasut · 7 years ago
  9. 325b7b9 clk: vc5: Do not warn about disabled output buffer input muxes by Marek Vasut · 7 years ago
  10. a4decf5 clk: vc5: Fix trivial typo by Marek Vasut · 7 years ago
  11. 3bded56 clk: vc5: Prevent division by zero on unconfigured outputs by Marek Vasut · 7 years ago
  12. 1193e14 clk: vc5: Add support for IDT VersaClock 5P49V5935 by Alexey Firago · 8 years ago
  13. 9adddb0 clk: vc5: Add structure to describe particular chip features by Alexey Firago · 8 years ago
  14. 3e1aec4e clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933 by Marek Vasut · 8 years ago