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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / 881994638c4033815dcdd26f43d209e83760d493 / . / arch / arm / boot / dts / imx53.dtsi
blob: 76ebb1ad2675334d38674fda586c9dee87d0cef8 [file] [log] [blame]
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]29 };
30
31 tzic: tz-interrupt-controller@0fffc000 {
32 compatible = "fsl,imx53-tzic", "fsl,tzic";
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 reg = <0x0fffc000 0x4000>;
36 };
37
38 clocks {
39 #address-cells = <1>;
40 #size-cells = <0>;
41
42 ckil {
43 compatible = "fsl,imx-ckil", "fixed-clock";
44 clock-frequency = <32768>;
45 };
46
47 ckih1 {
48 compatible = "fsl,imx-ckih1", "fixed-clock";
49 clock-frequency = <22579200>;
50 };
51
52 ckih2 {
53 compatible = "fsl,imx-ckih2", "fixed-clock";
54 clock-frequency = <0>;
55 };
56
57 osc {
58 compatible = "fsl,imx-osc", "fixed-clock";
59 clock-frequency = <24000000>;
60 };
61 };
62
63 soc {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "simple-bus";
67 interrupt-parent = <&tzic>;
68 ranges;
69
70 aips@50000000 { /* AIPS1 */
71 compatible = "fsl,aips-bus", "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 reg = <0x50000000 0x10000000>;
75 ranges;
76
77 spba@50000000 {
78 compatible = "fsl,spba-bus", "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 reg = <0x50000000 0x40000>;
82 ranges;
83
84 esdhc@50004000 { /* ESDHC1 */
85 compatible = "fsl,imx53-esdhc";
86 reg = <0x50004000 0x4000>;
87 interrupts = <1>;
88 status = "disabled";
89 };
90
91 esdhc@50008000 { /* ESDHC2 */
92 compatible = "fsl,imx53-esdhc";
93 reg = <0x50008000 0x4000>;
94 interrupts = <2>;
95 status = "disabled";
96 };
97
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]98 uart3: serial@5000c000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]99 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
100 reg = <0x5000c000 0x4000>;
101 interrupts = <33>;
102 status = "disabled";
103 };
104
105 ecspi@50010000 { /* ECSPI1 */
106 #address-cells = <1>;
107 #size-cells = <0>;
108 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
109 reg = <0x50010000 0x4000>;
110 interrupts = <36>;
111 status = "disabled";
112 };
113
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]114 ssi2: ssi@50014000 {
115 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
116 reg = <0x50014000 0x4000>;
117 interrupts = <30>;
118 fsl,fifo-depth = <15>;
119 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
120 status = "disabled";
121 };
122
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]123 esdhc@50020000 { /* ESDHC3 */
124 compatible = "fsl,imx53-esdhc";
125 reg = <0x50020000 0x4000>;
126 interrupts = <3>;
127 status = "disabled";
128 };
129
130 esdhc@50024000 { /* ESDHC4 */
131 compatible = "fsl,imx53-esdhc";
132 reg = <0x50024000 0x4000>;
133 interrupts = <4>;
134 status = "disabled";
135 };
136 };
137
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200[diff] [blame]138 usb@53f80000 {
139 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
140 reg = <0x53f80000 0x0200>;
141 interrupts = <18>;
142 status = "disabled";
143 };
144
145 usb@53f80200 {
146 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
147 reg = <0x53f80200 0x0200>;
148 interrupts = <14>;
149 status = "disabled";
150 };
151
152 usb@53f80400 {
153 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
154 reg = <0x53f80400 0x0200>;
155 interrupts = <16>;
156 status = "disabled";
157 };
158
159 usb@53f80600 {
160 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
161 reg = <0x53f80600 0x0200>;
162 interrupts = <17>;
163 status = "disabled";
164 };
165
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]166 gpio1: gpio@53f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]167 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]168 reg = <0x53f84000 0x4000>;
169 interrupts = <50 51>;
170 gpio-controller;
171 #gpio-cells = <2>;
172 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]173 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]174 };
175
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]176 gpio2: gpio@53f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]177 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]178 reg = <0x53f88000 0x4000>;
179 interrupts = <52 53>;
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]183 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]184 };
185
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]186 gpio3: gpio@53f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]187 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]188 reg = <0x53f8c000 0x4000>;
189 interrupts = <54 55>;
190 gpio-controller;
191 #gpio-cells = <2>;
192 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]193 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]194 };
195
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]196 gpio4: gpio@53f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]197 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]198 reg = <0x53f90000 0x4000>;
199 interrupts = <56 57>;
200 gpio-controller;
201 #gpio-cells = <2>;
202 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]203 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]204 };
205
206 wdog@53f98000 { /* WDOG1 */
207 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
208 reg = <0x53f98000 0x4000>;
209 interrupts = <58>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]210 };
211
212 wdog@53f9c000 { /* WDOG2 */
213 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
214 reg = <0x53f9c000 0x4000>;
215 interrupts = <59>;
216 status = "disabled";
217 };
218
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]219 iomuxc@53fa8000 {
220 compatible = "fsl,imx53-iomuxc";
221 reg = <0x53fa8000 0x4000>;
222
223 audmux {
224 pinctrl_audmux_1: audmuxgrp-1 {
225 fsl,pins = <
226 10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
227 17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
228 23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
229 30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
230 >;
231 };
232 };
233
234 fec {
235 pinctrl_fec_1: fecgrp-1 {
236 fsl,pins = <
237 820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
238 779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
239 786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
240 791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
241 796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
242 799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
243 804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
244 808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
245 811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
246 816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
247 >;
248 };
249 };
250
Shawn Guo327a79c2012-08-12 21:47:36 +0800[diff] [blame]251 ecspi1 {
252 pinctrl_ecspi1_1: ecspi1grp-1 {
253 fsl,pins = <
254 433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
255 439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
256 445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
257 >;
258 };
259 };
260
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]261 esdhc1 {
262 pinctrl_esdhc1_1: esdhc1grp-1 {
263 fsl,pins = <
264 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
265 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
266 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
267 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
268 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
269 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
270 >;
271 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]272
273 pinctrl_esdhc1_2: esdhc1grp-2 {
274 fsl,pins = <
275 995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
276 1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
277 1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
278 1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
279 941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
280 948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
281 955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
282 962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
283 1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
284 1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
285 >;
286 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]287 };
288
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]289 esdhc2 {
290 pinctrl_esdhc2_1: esdhc2grp-1 {
291 fsl,pins = <
292 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
293 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
294 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
295 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
296 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
297 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
298 >;
299 };
300 };
301
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]302 esdhc3 {
303 pinctrl_esdhc3_1: esdhc3grp-1 {
304 fsl,pins = <
305 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
306 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
307 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
308 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
309 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
310 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
311 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
312 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
313 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
314 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
315 >;
316 };
317 };
318
319 i2c1 {
320 pinctrl_i2c1_1: i2c1grp-1 {
321 fsl,pins = <
322 333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
323 341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
324 >;
325 };
326 };
327
328 i2c2 {
329 pinctrl_i2c2_1: i2c2grp-1 {
330 fsl,pins = <
331 61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
332 53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
333 >;
334 };
335 };
336
337 uart1 {
338 pinctrl_uart1_1: uart1grp-1 {
339 fsl,pins = <
340 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
341 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
342 >;
343 };
Shawn Guo4bb61432012-08-02 22:48:39 +0800[diff] [blame]344
345 pinctrl_uart1_2: uart1grp-2 {
346 fsl,pins = <
347 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
348 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
349 >;
350 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]351 };
Shawn Guo07248042012-08-12 22:22:33 +0800[diff] [blame]352
353 uart2 {
354 pinctrl_uart2_1: uart2grp-1 {
355 fsl,pins = <
356 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
357 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
358 >;
359 };
360 };
361
362 uart3 {
363 pinctrl_uart3_1: uart3grp-1 {
364 fsl,pins = <
365 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
366 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
367 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
368 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
369 >;
370 };
371 };
Shawn Guo5be03a72012-08-12 20:02:10 +0800[diff] [blame]372 };
373
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]374 uart1: serial@53fbc000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]375 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
376 reg = <0x53fbc000 0x4000>;
377 interrupts = <31>;
378 status = "disabled";
379 };
380
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]381 uart2: serial@53fc0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]382 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
383 reg = <0x53fc0000 0x4000>;
384 interrupts = <32>;
385 status = "disabled";
386 };
387
Steffen Trumtrara9d1f922012-07-18 11:42:43 +0200[diff] [blame]388 can1: can@53fc8000 {
389 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
390 reg = <0x53fc8000 0x4000>;
391 interrupts = <82>;
392 status = "disabled";
393 };
394
395 can2: can@53fcc000 {
396 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
397 reg = <0x53fcc000 0x4000>;
398 interrupts = <83>;
399 status = "disabled";
400 };
401
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]402 gpio5: gpio@53fdc000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]403 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]404 reg = <0x53fdc000 0x4000>;
405 interrupts = <103 104>;
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]409 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]410 };
411
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]412 gpio6: gpio@53fe0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]413 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]414 reg = <0x53fe0000 0x4000>;
415 interrupts = <105 106>;
416 gpio-controller;
417 #gpio-cells = <2>;
418 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]419 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]420 };
421
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]422 gpio7: gpio@53fe4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]423 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]424 reg = <0x53fe4000 0x4000>;
425 interrupts = <107 108>;
426 gpio-controller;
427 #gpio-cells = <2>;
428 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]429 #interrupt-cells = <2>;
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]430 };
431
432 i2c@53fec000 { /* I2C3 */
433 #address-cells = <1>;
434 #size-cells = <0>;
435 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
436 reg = <0x53fec000 0x4000>;
437 interrupts = <64>;
438 status = "disabled";
439 };
440
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]441 uart4: serial@53ff0000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]442 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
443 reg = <0x53ff0000 0x4000>;
444 interrupts = <13>;
445 status = "disabled";
446 };
447 };
448
449 aips@60000000 { /* AIPS2 */
450 compatible = "fsl,aips-bus", "simple-bus";
451 #address-cells = <1>;
452 #size-cells = <1>;
453 reg = <0x60000000 0x10000000>;
454 ranges;
455
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]456 uart5: serial@63f90000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]457 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
458 reg = <0x63f90000 0x4000>;
459 interrupts = <86>;
460 status = "disabled";
461 };
462
463 ecspi@63fac000 { /* ECSPI2 */
464 #address-cells = <1>;
465 #size-cells = <0>;
466 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
467 reg = <0x63fac000 0x4000>;
468 interrupts = <37>;
469 status = "disabled";
470 };
471
472 sdma@63fb0000 {
473 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
474 reg = <0x63fb0000 0x4000>;
475 interrupts = <6>;
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300[diff] [blame]476 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]477 };
478
479 cspi@63fc0000 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
483 reg = <0x63fc0000 0x4000>;
484 interrupts = <38>;
485 status = "disabled";
486 };
487
488 i2c@63fc4000 { /* I2C2 */
489 #address-cells = <1>;
490 #size-cells = <0>;
491 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
492 reg = <0x63fc4000 0x4000>;
493 interrupts = <63>;
494 status = "disabled";
495 };
496
497 i2c@63fc8000 { /* I2C1 */
498 #address-cells = <1>;
499 #size-cells = <0>;
500 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
501 reg = <0x63fc8000 0x4000>;
502 interrupts = <62>;
503 status = "disabled";
504 };
505
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]506 ssi1: ssi@63fcc000 {
507 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
508 reg = <0x63fcc000 0x4000>;
509 interrupts = <29>;
510 fsl,fifo-depth = <15>;
511 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
512 status = "disabled";
513 };
514
515 audmux@63fd0000 {
516 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
517 reg = <0x63fd0000 0x4000>;
518 status = "disabled";
519 };
520
Sascha Hauer75453a02012-06-06 12:33:16 +0200[diff] [blame]521 nand@63fdb000 {
522 compatible = "fsl,imx53-nand";
523 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
524 interrupts = <8>;
525 status = "disabled";
526 };
527
Shawn Guoffc505c2012-05-11 13:12:01 +0800[diff] [blame]528 ssi3: ssi@63fe8000 {
529 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
530 reg = <0x63fe8000 0x4000>;
531 interrupts = <96>;
532 fsl,fifo-depth = <15>;
533 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
534 status = "disabled";
535 };
536
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]537 ethernet@63fec000 {
Shawn Guo73d2b4c2011-10-17 08:42:16 +0800[diff] [blame]538 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
539 reg = <0x63fec000 0x4000>;
540 interrupts = <87>;
541 status = "disabled";
542 };
543 };
544 };
545};