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Adam Lee522624f2013-12-18 22:23:38 +08001#ifndef __SDHCI_PCI_H
2#define __SDHCI_PCI_H
3
4/*
5 * PCI device IDs
6 */
7
8#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
9#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
10#define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
11#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
12#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
13#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
Alan Cox066173b2014-08-20 13:27:44 +030014#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
15#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
16#define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
Adam Lee522624f2013-12-18 22:23:38 +080017#define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190
18#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
19#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
20#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
21#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
22#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
Derek Browne43e968c2014-06-24 06:56:36 -070023#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
Adrian Hunter1f7f2652015-01-05 14:47:58 +020024#define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
25#define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
26#define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
Adrian Hunter06bf9c52015-10-06 10:26:21 +030027#define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db
Adam Lee522624f2013-12-18 22:23:38 +080028
29/*
30 * PCI registers
31 */
32
33#define PCI_SDHCI_IFPIO 0x00
34#define PCI_SDHCI_IFDMA 0x01
35#define PCI_SDHCI_IFVENDOR 0x02
36
37#define PCI_SLOT_INFO 0x40 /* 8 bits */
38#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
39#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
40
41#define MAX_SLOTS 8
42
43struct sdhci_pci_chip;
44struct sdhci_pci_slot;
45
46struct sdhci_pci_fixes {
47 unsigned int quirks;
48 unsigned int quirks2;
49 bool allow_runtime_pm;
Adrian Hunter77a01222014-01-13 09:49:16 +020050 bool own_cd_for_runtime_pm;
Adam Lee522624f2013-12-18 22:23:38 +080051
52 int (*probe) (struct sdhci_pci_chip *);
53
54 int (*probe_slot) (struct sdhci_pci_slot *);
55 void (*remove_slot) (struct sdhci_pci_slot *, int);
56
57 int (*suspend) (struct sdhci_pci_chip *);
58 int (*resume) (struct sdhci_pci_chip *);
59};
60
61struct sdhci_pci_slot {
62 struct sdhci_pci_chip *chip;
63 struct sdhci_host *host;
64 struct sdhci_pci_data *data;
65
66 int pci_bar;
67 int rst_n_gpio;
68 int cd_gpio;
69 int cd_irq;
70
Adrian Hunterff59c522014-09-24 10:27:31 +030071 char *cd_con_id;
72 int cd_idx;
73 bool cd_override_level;
74
Adam Lee522624f2013-12-18 22:23:38 +080075 void (*hw_reset)(struct sdhci_host *host);
Adrian Huntere1bfad62015-02-06 14:13:00 +020076 int (*select_drive_strength)(struct sdhci_host *host,
77 struct mmc_card *card,
78 unsigned int max_dtr, int host_drv,
79 int card_drv, int *drv_type);
Adam Lee522624f2013-12-18 22:23:38 +080080};
81
82struct sdhci_pci_chip {
83 struct pci_dev *pdev;
84
85 unsigned int quirks;
86 unsigned int quirks2;
87 bool allow_runtime_pm;
88 const struct sdhci_pci_fixes *fixes;
89
90 int num_slots; /* Slots on controller */
91 struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
92};
93
94#endif /* __SDHCI_PCI_H */