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review.shift-gmbh.com / SHIFTPHONES / kernel / shift / mainline / d0fc2eaaf4c56a95f5ed29b6bfb609e19714fc16 / . / arch / powerpc / boot / dts / mpc8544ds.dts
blob: 6cf533f4b5fb94390d22c74454e868f19ff8991c [file] [log] [blame]
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]1/*
2 * MPC8544 DS Device Tree Source
3 *
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]12/dts-v1/;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]13/ {
14 model = "MPC8544DS";
15 compatible = "MPC8544DS", "MPC85xxDS";
16 #address-cells = <1>;
17 #size-cells = <1>;
18
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 serial0 = &serial0;
23 serial1 = &serial1;
24 pci0 = &pci0;
25 pci1 = &pci1;
26 pci2 = &pci2;
27 pci3 = &pci3;
28 };
29
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]30 cpus {
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,8544@0 {
35 device_type = "cpu";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]36 reg = <0x0>;
37 d-cache-line-size = <32>; // 32 bytes
38 i-cache-line-size = <32>; // 32 bytes
39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]41 timebase-frequency = <0>;
42 bus-frequency = <0>;
43 clock-frequency = <0>;
Kumar Galac0540652008-05-30 13:43:43 -0500[diff] [blame]44 next-level-cache = <&L2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]45 };
46 };
47
48 memory {
49 device_type = "memory";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]50 reg = <0x0 0x0>; // Filled by U-Boot
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]51 };
52
53 soc8544@e0000000 {
54 #address-cells = <1>;
55 #size-cells = <1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]56 device_type = "soc";
Kumar Galab66510c2007-08-16 23:55:55 -0500[diff] [blame]57
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]58 ranges = <0x0 0xe0000000 0x100000>;
59 reg = <0xe0000000 0x1000>; // CCSRBAR 1M
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]60 bus-frequency = <0>; // Filled out by uboot.
61
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]62 memory-controller@2000 {
63 compatible = "fsl,8544-memory-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]64 reg = <0x2000 0x1000>;
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]65 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]66 interrupts = <18 2>;
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]67 };
68
Kumar Galac0540652008-05-30 13:43:43 -0500[diff] [blame]69 L2: l2-cache-controller@20000 {
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]70 compatible = "fsl,8544-l2-cache-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]71 reg = <0x20000 0x1000>;
72 cache-line-size = <32>; // 32 bytes
73 cache-size = <0x40000>; // L2, 256K
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]74 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]75 interrupts = <16 2>;
Kumar Gala4da421d2007-05-15 13:20:05 -0500[diff] [blame]76 };
77
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]78 i2c@3000 {
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]79 #address-cells = <1>;
80 #size-cells = <0>;
81 cell-index = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]82 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]83 reg = <0x3000 0x100>;
84 interrupts = <43 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]85 interrupt-parent = <&mpic>;
86 dfsrr;
87 };
88
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]89 i2c@3100 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 cell-index = <1>;
93 compatible = "fsl-i2c";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]94 reg = <0x3100 0x100>;
95 interrupts = <43 2>;
Kumar Galaec9686c2007-12-11 23:17:24 -0600[diff] [blame]96 interrupt-parent = <&mpic>;
97 dfsrr;
98 };
99
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]100 mdio@24520 {
101 #address-cells = <1>;
102 #size-cells = <0>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]103 compatible = "fsl,gianfar-mdio";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]104 reg = <0x24520 0x20>;
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]105
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]106 phy0: ethernet-phy@0 {
107 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]108 interrupts = <10 1>;
109 reg = <0x0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]110 device_type = "ethernet-phy";
111 };
112 phy1: ethernet-phy@1 {
113 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]114 interrupts = <10 1>;
115 reg = <0x1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]116 device_type = "ethernet-phy";
117 };
118 };
119
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]120 dma@21300 {
121 #address-cells = <1>;
122 #size-cells = <1>;
123 compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]124 reg = <0x21300 0x4>;
125 ranges = <0x0 0x21100 0x200>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]126 cell-index = <0>;
127 dma-channel@0 {
128 compatible = "fsl,mpc8544-dma-channel",
129 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]130 reg = <0x0 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]131 cell-index = <0>;
132 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]133 interrupts = <20 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]134 };
135 dma-channel@80 {
136 compatible = "fsl,mpc8544-dma-channel",
137 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]138 reg = <0x80 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]139 cell-index = <1>;
140 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]141 interrupts = <21 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]142 };
143 dma-channel@100 {
144 compatible = "fsl,mpc8544-dma-channel",
145 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]146 reg = <0x100 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]147 cell-index = <2>;
148 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]149 interrupts = <22 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]150 };
151 dma-channel@180 {
152 compatible = "fsl,mpc8544-dma-channel",
153 "fsl,eloplus-dma-channel";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]154 reg = <0x180 0x80>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]155 cell-index = <3>;
156 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]157 interrupts = <23 2>;
Sebastian Siewior1028d4f2008-03-15 00:01:30 +0100[diff] [blame]158 };
159 };
160
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]161 enet0: ethernet@24000 {
162 cell-index = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]163 device_type = "network";
164 model = "TSEC";
165 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]166 reg = <0x24000 0x1000>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]167 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]168 interrupts = <29 2 30 2 34 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]169 interrupt-parent = <&mpic>;
170 phy-handle = <&phy0>;
Kumar Gala9a9bcf42007-07-26 00:07:36 -0500[diff] [blame]171 phy-connection-type = "rgmii-id";
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]172 };
173
Kumar Galae77b28e2007-12-12 00:28:35 -0600[diff] [blame]174 enet1: ethernet@26000 {
175 cell-index = <1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]176 device_type = "network";
177 model = "TSEC";
178 compatible = "gianfar";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]179 reg = <0x26000 0x1000>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]180 local-mac-address = [ 00 00 00 00 00 00 ];
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]181 interrupts = <31 2 32 2 33 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]182 interrupt-parent = <&mpic>;
183 phy-handle = <&phy1>;
Kumar Gala9a9bcf42007-07-26 00:07:36 -0500[diff] [blame]184 phy-connection-type = "rgmii-id";
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]185 };
186
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]187 serial0: serial@4500 {
188 cell-index = <0>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]189 device_type = "serial";
190 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]191 reg = <0x4500 0x100>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]192 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]193 interrupts = <42 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]194 interrupt-parent = <&mpic>;
195 };
196
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]197 serial1: serial@4600 {
198 cell-index = <1>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]199 device_type = "serial";
200 compatible = "ns16550";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]201 reg = <0x4600 0x100>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]202 clock-frequency = <0>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]203 interrupts = <42 2>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]204 interrupt-parent = <&mpic>;
205 };
206
Roy Zang10ce8c62007-07-13 17:35:33 +0800[diff] [blame]207 global-utilities@e0000 { //global utilities block
208 compatible = "fsl,mpc8548-guts";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]209 reg = <0xe0000 0x1000>;
Roy Zang10ce8c62007-07-13 17:35:33 +0800[diff] [blame]210 fsl,has-rstcr;
211 };
212
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]213 mpic: pic@40000 {
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]214 interrupt-controller;
215 #address-cells = <0>;
216 #interrupt-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]217 reg = <0x40000 0x40000>;
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]218 compatible = "chrp,open-pic";
219 device_type = "open-pic";
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]220 };
Jason Jin741edc42008-05-23 16:32:48 +0800[diff] [blame]221
222 msi@41600 {
223 compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
224 reg = <0x41600 0x80>;
225 msi-available-ranges = <0 0x100>;
226 interrupts = <
227 0xe0 0
228 0xe1 0
229 0xe2 0
230 0xe3 0
231 0xe4 0
232 0xe5 0
233 0xe6 0
234 0xe7 0>;
235 interrupt-parent = <&mpic>;
236 };
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]237 };
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]238
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]239 pci0: pci@e0008000 {
240 cell-index = <0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]241 compatible = "fsl,mpc8540-pci";
242 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]243 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]244 interrupt-map = <
245
246 /* IDSEL 0x11 J17 Slot 1 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]247 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
248 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
249 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
250 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]251
252 /* IDSEL 0x12 J16 Slot 2 */
253
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]254 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
255 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
256 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
257 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]258
259 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]260 interrupts = <24 2>;
261 bus-range = <0 255>;
262 ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
263 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
264 clock-frequency = <66666666>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]265 #interrupt-cells = <1>;
266 #size-cells = <2>;
267 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]268 reg = <0xe0008000 0x1000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]269 };
270
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]271 pci1: pcie@e0009000 {
272 cell-index = <1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]273 compatible = "fsl,mpc8548-pcie";
274 device_type = "pci";
275 #interrupt-cells = <1>;
276 #size-cells = <2>;
277 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]278 reg = <0xe0009000 0x1000>;
279 bus-range = <0 255>;
280 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
281 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
282 clock-frequency = <33333333>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]283 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]284 interrupts = <26 2>;
285 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]286 interrupt-map = <
287 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]288 0000 0x0 0x0 0x1 &mpic 0x4 0x1
289 0000 0x0 0x0 0x2 &mpic 0x5 0x1
290 0000 0x0 0x0 0x3 &mpic 0x6 0x1
291 0000 0x0 0x0 0x4 &mpic 0x7 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]292 >;
293 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]294 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]295 #size-cells = <2>;
296 #address-cells = <3>;
297 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]298 ranges = <0x2000000 0x0 0x80000000
299 0x2000000 0x0 0x80000000
300 0x0 0x20000000
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]301
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]302 0x1000000 0x0 0x0
303 0x1000000 0x0 0x0
304 0x0 0x10000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]305 };
306 };
307
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]308 pci2: pcie@e000a000 {
309 cell-index = <2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]310 compatible = "fsl,mpc8548-pcie";
311 device_type = "pci";
312 #interrupt-cells = <1>;
313 #size-cells = <2>;
314 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]315 reg = <0xe000a000 0x1000>;
316 bus-range = <0 255>;
317 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
318 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
319 clock-frequency = <33333333>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]320 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]321 interrupts = <25 2>;
322 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]323 interrupt-map = <
324 /* IDSEL 0x0 */
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]325 0000 0x0 0x0 0x1 &mpic 0x0 0x1
326 0000 0x0 0x0 0x2 &mpic 0x1 0x1
327 0000 0x0 0x0 0x3 &mpic 0x2 0x1
328 0000 0x0 0x0 0x4 &mpic 0x3 0x1
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]329 >;
330 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]331 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]332 #size-cells = <2>;
333 #address-cells = <3>;
334 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]335 ranges = <0x2000000 0x0 0xa0000000
336 0x2000000 0x0 0xa0000000
337 0x0 0x10000000
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]338
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]339 0x1000000 0x0 0x0
340 0x1000000 0x0 0x0
341 0x0 0x10000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]342 };
343 };
344
Kumar Galaea082fa2007-12-12 01:46:12 -0600[diff] [blame]345 pci3: pcie@e000b000 {
346 cell-index = <3>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]347 compatible = "fsl,mpc8548-pcie";
348 device_type = "pci";
349 #interrupt-cells = <1>;
350 #size-cells = <2>;
351 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]352 reg = <0xe000b000 0x1000>;
353 bus-range = <0 255>;
354 ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
355 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
356 clock-frequency = <33333333>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]357 interrupt-parent = <&mpic>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]358 interrupts = <27 2>;
359 interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]360 interrupt-map = <
361 // IDSEL 0x1c USB
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]362 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
363 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
364 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
365 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]366
367 // IDSEL 0x1d Audio
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]368 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]369
370 // IDSEL 0x1e Legacy
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]371 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
372 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]373
374 // IDSEL 0x1f IDE/SATA
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]375 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
376 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]377 >;
378
379 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]380 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]381 #size-cells = <2>;
382 #address-cells = <3>;
383 device_type = "pci";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]384 ranges = <0x2000000 0x0 0xb0000000
385 0x2000000 0x0 0xb0000000
386 0x0 0x100000
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]387
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]388 0x1000000 0x0 0x0
389 0x1000000 0x0 0x0
390 0x0 0x100000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]391
392 uli1575@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]393 reg = <0x0 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]394 #size-cells = <2>;
395 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]396 ranges = <0x2000000 0x0 0xb0000000
397 0x2000000 0x0 0xb0000000
398 0x0 0x100000
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]399
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]400 0x1000000 0x0 0x0
401 0x1000000 0x0 0x0
402 0x0 0x100000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]403 isa@1e {
404 device_type = "isa";
405 #interrupt-cells = <2>;
406 #size-cells = <1>;
407 #address-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]408 reg = <0xf000 0x0 0x0 0x0 0x0>;
409 ranges = <0x1 0x0
410 0x1000000 0x0 0x0
411 0x1000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]412 interrupt-parent = <&i8259>;
413
414 i8259: interrupt-controller@20 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]415 reg = <0x1 0x20 0x2
416 0x1 0xa0 0x2
417 0x1 0x4d0 0x2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]418 interrupt-controller;
419 device_type = "interrupt-controller";
420 #address-cells = <0>;
421 #interrupt-cells = <2>;
422 compatible = "chrp,iic";
423 interrupts = <9 2>;
424 interrupt-parent = <&mpic>;
425 };
426
427 i8042@60 {
428 #size-cells = <0>;
429 #address-cells = <1>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]430 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
431 interrupts = <1 3 12 3>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]432 interrupt-parent = <&i8259>;
433
434 keyboard@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]435 reg = <0x0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]436 compatible = "pnpPNP,303";
437 };
438
439 mouse@1 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]440 reg = <0x1>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]441 compatible = "pnpPNP,f03";
442 };
443 };
444
445 rtc@70 {
446 compatible = "pnpPNP,b00";
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]447 reg = <0x1 0x70 0x2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]448 };
449
450 gpio@400 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500[diff] [blame]451 reg = <0x1 0x400 0x80>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]452 };
453 };
454 };
455 };
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500[diff] [blame]456 };
Jon Loeligerd93daf82007-03-20 11:19:10 -0500[diff] [blame]457};