blob: 30762734d859a3525bafe744378268d8477f73e4 [file] [log] [blame]
Jeeja KPd255b092015-07-21 23:53:56 +05301/*
2 * skl-message.c - HDA DSP interface for FW registration, Pipe and Module
3 * configurations
4 *
5 * Copyright (C) 2015 Intel Corp
6 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
7 * Jeeja KP <jeeja.kp@intel.com>
8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 */
19
20#include <linux/slab.h>
21#include <linux/pci.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include "skl-sst-dsp.h"
25#include "skl-sst-ipc.h"
26#include "skl.h"
27#include "../common/sst-dsp.h"
28#include "../common/sst-dsp-priv.h"
Jeeja KP23db4722015-08-01 19:40:41 +053029#include "skl-topology.h"
30#include "skl-tplg-interface.h"
Jeeja KPd255b092015-07-21 23:53:56 +053031
32static int skl_alloc_dma_buf(struct device *dev,
33 struct snd_dma_buffer *dmab, size_t size)
34{
35 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
36 struct hdac_bus *bus = ebus_to_hbus(ebus);
37
38 if (!bus)
39 return -ENODEV;
40
41 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV, size, dmab);
42}
43
44static int skl_free_dma_buf(struct device *dev, struct snd_dma_buffer *dmab)
45{
46 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
47 struct hdac_bus *bus = ebus_to_hbus(ebus);
48
49 if (!bus)
50 return -ENODEV;
51
52 bus->io_ops->dma_free_pages(bus, dmab);
53
54 return 0;
55}
56
Jeeja KP4e109962015-10-22 23:22:39 +053057#define NOTIFICATION_PARAM_ID 3
58#define NOTIFICATION_MASK 0xf
59
60/* disable notfication for underruns/overruns from firmware module */
61static void skl_dsp_enable_notification(struct skl_sst *ctx, bool enable)
62{
63 struct notification_mask mask;
64 struct skl_ipc_large_config_msg msg = {0};
65
66 mask.notify = NOTIFICATION_MASK;
67 mask.enable = enable;
68
69 msg.large_param_id = NOTIFICATION_PARAM_ID;
70 msg.param_data_size = sizeof(mask);
71
72 skl_ipc_set_large_config(&ctx->ipc, &msg, (u32 *)&mask);
73}
74
Jeeja KPd255b092015-07-21 23:53:56 +053075int skl_init_dsp(struct skl *skl)
76{
77 void __iomem *mmio_base;
78 struct hdac_ext_bus *ebus = &skl->ebus;
79 struct hdac_bus *bus = ebus_to_hbus(ebus);
80 int irq = bus->irq;
81 struct skl_dsp_loader_ops loader_ops;
82 int ret;
83
84 loader_ops.alloc_dma_buf = skl_alloc_dma_buf;
85 loader_ops.free_dma_buf = skl_free_dma_buf;
86
87 /* enable ppcap interrupt */
88 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true);
89 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true);
90
91 /* read the BAR of the ADSP MMIO */
92 mmio_base = pci_ioremap_bar(skl->pci, 4);
93 if (mmio_base == NULL) {
94 dev_err(bus->dev, "ioremap error\n");
95 return -ENXIO;
96 }
97
98 ret = skl_sst_dsp_init(bus->dev, mmio_base, irq,
Vinod Koulaecf6fd2015-11-05 21:34:15 +053099 skl->fw_name, loader_ops, &skl->skl_sst);
Jeeja KP2ac454f2015-10-22 23:22:40 +0530100 if (ret < 0)
101 return ret;
102
Jeeja KP4e109962015-10-22 23:22:39 +0530103 skl_dsp_enable_notification(skl->skl_sst, false);
Jeeja KPd255b092015-07-21 23:53:56 +0530104 dev_dbg(bus->dev, "dsp registration status=%d\n", ret);
105
106 return ret;
107}
108
109void skl_free_dsp(struct skl *skl)
110{
111 struct hdac_ext_bus *ebus = &skl->ebus;
112 struct hdac_bus *bus = ebus_to_hbus(ebus);
113 struct skl_sst *ctx = skl->skl_sst;
114
115 /* disable ppcap interrupt */
116 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false);
117
118 skl_sst_dsp_cleanup(bus->dev, ctx);
119 if (ctx->dsp->addr.lpe)
120 iounmap(ctx->dsp->addr.lpe);
121}
122
123int skl_suspend_dsp(struct skl *skl)
124{
125 struct skl_sst *ctx = skl->skl_sst;
126 int ret;
127
128 /* if ppcap is not supported return 0 */
129 if (!skl->ebus.ppcap)
130 return 0;
131
132 ret = skl_dsp_sleep(ctx->dsp);
133 if (ret < 0)
134 return ret;
135
136 /* disable ppcap interrupt */
137 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, false);
138 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, false);
139
140 return 0;
141}
142
143int skl_resume_dsp(struct skl *skl)
144{
145 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP4e109962015-10-22 23:22:39 +0530146 int ret;
Jeeja KPd255b092015-07-21 23:53:56 +0530147
148 /* if ppcap is not supported return 0 */
149 if (!skl->ebus.ppcap)
150 return 0;
151
152 /* enable ppcap interrupt */
153 snd_hdac_ext_bus_ppcap_enable(&skl->ebus, true);
154 snd_hdac_ext_bus_ppcap_int_enable(&skl->ebus, true);
155
Jeeja KP4e109962015-10-22 23:22:39 +0530156 ret = skl_dsp_wake(ctx->dsp);
157 if (ret < 0)
158 return ret;
159
160 skl_dsp_enable_notification(skl->skl_sst, false);
161 return ret;
Jeeja KPd255b092015-07-21 23:53:56 +0530162}
Jeeja KP23db4722015-08-01 19:40:41 +0530163
164enum skl_bitdepth skl_get_bit_depth(int params)
165{
166 switch (params) {
167 case 8:
168 return SKL_DEPTH_8BIT;
169
170 case 16:
171 return SKL_DEPTH_16BIT;
172
173 case 24:
174 return SKL_DEPTH_24BIT;
175
176 case 32:
177 return SKL_DEPTH_32BIT;
178
179 default:
180 return SKL_DEPTH_INVALID;
181
182 }
183}
184
Jeeja KP23db4722015-08-01 19:40:41 +0530185/*
186 * Each module in DSP expects a base module configuration, which consists of
187 * PCM format information, which we calculate in driver and resource values
188 * which are read from widget information passed through topology binary
189 * This is send when we create a module with INIT_INSTANCE IPC msg
190 */
191static void skl_set_base_module_format(struct skl_sst *ctx,
192 struct skl_module_cfg *mconfig,
193 struct skl_base_cfg *base_cfg)
194{
Hardik T Shah4cd98992015-10-27 09:22:55 +0900195 struct skl_module_fmt *format = &mconfig->in_fmt[0];
Jeeja KP23db4722015-08-01 19:40:41 +0530196
197 base_cfg->audio_fmt.number_of_channels = (u8)format->channels;
198
199 base_cfg->audio_fmt.s_freq = format->s_freq;
200 base_cfg->audio_fmt.bit_depth = format->bit_depth;
201 base_cfg->audio_fmt.valid_bit_depth = format->valid_bit_depth;
202 base_cfg->audio_fmt.ch_cfg = format->ch_cfg;
203
204 dev_dbg(ctx->dev, "bit_depth=%x valid_bd=%x ch_config=%x\n",
205 format->bit_depth, format->valid_bit_depth,
206 format->ch_cfg);
207
Jeeja KP3e81f1a2015-10-27 09:22:59 +0900208 base_cfg->audio_fmt.channel_map = format->ch_map;
Jeeja KP23db4722015-08-01 19:40:41 +0530209
Jeeja KP3e81f1a2015-10-27 09:22:59 +0900210 base_cfg->audio_fmt.interleaving = format->interleaving_style;
Jeeja KP23db4722015-08-01 19:40:41 +0530211
212 base_cfg->cps = mconfig->mcps;
213 base_cfg->ibs = mconfig->ibs;
214 base_cfg->obs = mconfig->obs;
215}
216
217/*
218 * Copies copier capabilities into copier module and updates copier module
219 * config size.
220 */
221static void skl_copy_copier_caps(struct skl_module_cfg *mconfig,
222 struct skl_cpr_cfg *cpr_mconfig)
223{
224 if (mconfig->formats_config.caps_size == 0)
225 return;
226
227 memcpy(cpr_mconfig->gtw_cfg.config_data,
228 mconfig->formats_config.caps,
229 mconfig->formats_config.caps_size);
230
231 cpr_mconfig->gtw_cfg.config_length =
232 (mconfig->formats_config.caps_size) / 4;
233}
234
Jeeja KPbfa764a2015-10-22 23:22:41 +0530235#define SKL_NON_GATEWAY_CPR_NODE_ID 0xFFFFFFFF
Jeeja KP23db4722015-08-01 19:40:41 +0530236/*
237 * Calculate the gatewat settings required for copier module, type of
238 * gateway and index of gateway to use
239 */
240static void skl_setup_cpr_gateway_cfg(struct skl_sst *ctx,
241 struct skl_module_cfg *mconfig,
242 struct skl_cpr_cfg *cpr_mconfig)
243{
244 union skl_connector_node_id node_id = {0};
Jeeja KPd7b18812015-10-22 23:22:38 +0530245 union skl_ssp_dma_node ssp_node = {0};
Jeeja KP23db4722015-08-01 19:40:41 +0530246 struct skl_pipe_params *params = mconfig->pipe->p_params;
247
248 switch (mconfig->dev_type) {
249 case SKL_DEVICE_BT:
250 node_id.node.dma_type =
251 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
252 SKL_DMA_I2S_LINK_OUTPUT_CLASS :
253 SKL_DMA_I2S_LINK_INPUT_CLASS;
254 node_id.node.vindex = params->host_dma_id +
255 (mconfig->vbus_id << 3);
256 break;
257
258 case SKL_DEVICE_I2S:
259 node_id.node.dma_type =
260 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
261 SKL_DMA_I2S_LINK_OUTPUT_CLASS :
262 SKL_DMA_I2S_LINK_INPUT_CLASS;
Jeeja KPd7b18812015-10-22 23:22:38 +0530263 ssp_node.dma_node.time_slot_index = mconfig->time_slot;
264 ssp_node.dma_node.i2s_instance = mconfig->vbus_id;
265 node_id.node.vindex = ssp_node.val;
Jeeja KP23db4722015-08-01 19:40:41 +0530266 break;
267
268 case SKL_DEVICE_DMIC:
269 node_id.node.dma_type = SKL_DMA_DMIC_LINK_INPUT_CLASS;
270 node_id.node.vindex = mconfig->vbus_id +
271 (mconfig->time_slot);
272 break;
273
274 case SKL_DEVICE_HDALINK:
275 node_id.node.dma_type =
276 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
277 SKL_DMA_HDA_LINK_OUTPUT_CLASS :
278 SKL_DMA_HDA_LINK_INPUT_CLASS;
279 node_id.node.vindex = params->link_dma_id;
280 break;
281
Jeeja KPbfa764a2015-10-22 23:22:41 +0530282 case SKL_DEVICE_HDAHOST:
Jeeja KP23db4722015-08-01 19:40:41 +0530283 node_id.node.dma_type =
284 (SKL_CONN_SOURCE == mconfig->hw_conn_type) ?
285 SKL_DMA_HDA_HOST_OUTPUT_CLASS :
286 SKL_DMA_HDA_HOST_INPUT_CLASS;
287 node_id.node.vindex = params->host_dma_id;
288 break;
Jeeja KPbfa764a2015-10-22 23:22:41 +0530289
290 default:
291 cpr_mconfig->gtw_cfg.node_id = SKL_NON_GATEWAY_CPR_NODE_ID;
292 cpr_mconfig->cpr_feature_mask = 0;
293 return;
Jeeja KP23db4722015-08-01 19:40:41 +0530294 }
295
296 cpr_mconfig->gtw_cfg.node_id = node_id.val;
297
298 if (SKL_CONN_SOURCE == mconfig->hw_conn_type)
299 cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * mconfig->obs;
300 else
301 cpr_mconfig->gtw_cfg.dma_buffer_size = 2 * mconfig->ibs;
302
303 cpr_mconfig->cpr_feature_mask = 0;
304 cpr_mconfig->gtw_cfg.config_length = 0;
305
306 skl_copy_copier_caps(mconfig, cpr_mconfig);
307}
308
309static void skl_setup_out_format(struct skl_sst *ctx,
310 struct skl_module_cfg *mconfig,
311 struct skl_audio_data_format *out_fmt)
312{
Hardik T Shah4cd98992015-10-27 09:22:55 +0900313 struct skl_module_fmt *format = &mconfig->out_fmt[0];
Jeeja KP23db4722015-08-01 19:40:41 +0530314
315 out_fmt->number_of_channels = (u8)format->channels;
316 out_fmt->s_freq = format->s_freq;
317 out_fmt->bit_depth = format->bit_depth;
318 out_fmt->valid_bit_depth = format->valid_bit_depth;
319 out_fmt->ch_cfg = format->ch_cfg;
320
Jeeja KP3e81f1a2015-10-27 09:22:59 +0900321 out_fmt->channel_map = format->ch_map;
322 out_fmt->interleaving = format->interleaving_style;
323 out_fmt->sample_type = format->sample_type;
Jeeja KP23db4722015-08-01 19:40:41 +0530324
325 dev_dbg(ctx->dev, "copier out format chan=%d fre=%d bitdepth=%d\n",
326 out_fmt->number_of_channels, format->s_freq, format->bit_depth);
327}
328
329/*
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530330 * DSP needs SRC module for frequency conversion, SRC takes base module
331 * configuration and the target frequency as extra parameter passed as src
332 * config
333 */
334static void skl_set_src_format(struct skl_sst *ctx,
335 struct skl_module_cfg *mconfig,
336 struct skl_src_module_cfg *src_mconfig)
337{
Hardik T Shah4cd98992015-10-27 09:22:55 +0900338 struct skl_module_fmt *fmt = &mconfig->out_fmt[0];
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530339
340 skl_set_base_module_format(ctx, mconfig,
341 (struct skl_base_cfg *)src_mconfig);
342
343 src_mconfig->src_cfg = fmt->s_freq;
344}
345
346/*
347 * DSP needs updown module to do channel conversion. updown module take base
348 * module configuration and channel configuration
349 * It also take coefficients and now we have defaults applied here
350 */
351static void skl_set_updown_mixer_format(struct skl_sst *ctx,
352 struct skl_module_cfg *mconfig,
353 struct skl_up_down_mixer_cfg *mixer_mconfig)
354{
Hardik T Shah4cd98992015-10-27 09:22:55 +0900355 struct skl_module_fmt *fmt = &mconfig->out_fmt[0];
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530356 int i = 0;
357
358 skl_set_base_module_format(ctx, mconfig,
359 (struct skl_base_cfg *)mixer_mconfig);
360 mixer_mconfig->out_ch_cfg = fmt->ch_cfg;
361
362 /* Select F/W default coefficient */
363 mixer_mconfig->coeff_sel = 0x0;
364
365 /* User coeff, don't care since we are selecting F/W defaults */
366 for (i = 0; i < UP_DOWN_MIXER_MAX_COEFF; i++)
367 mixer_mconfig->coeff[i] = 0xDEADBEEF;
368}
369
370/*
Jeeja KP23db4722015-08-01 19:40:41 +0530371 * 'copier' is DSP internal module which copies data from Host DMA (HDA host
372 * dma) or link (hda link, SSP, PDM)
373 * Here we calculate the copier module parameters, like PCM format, output
374 * format, gateway settings
375 * copier_module_config is sent as input buffer with INIT_INSTANCE IPC msg
376 */
377static void skl_set_copier_format(struct skl_sst *ctx,
378 struct skl_module_cfg *mconfig,
379 struct skl_cpr_cfg *cpr_mconfig)
380{
381 struct skl_audio_data_format *out_fmt = &cpr_mconfig->out_fmt;
382 struct skl_base_cfg *base_cfg = (struct skl_base_cfg *)cpr_mconfig;
383
384 skl_set_base_module_format(ctx, mconfig, base_cfg);
385
386 skl_setup_out_format(ctx, mconfig, out_fmt);
387 skl_setup_cpr_gateway_cfg(ctx, mconfig, cpr_mconfig);
388}
389
390static u16 skl_get_module_param_size(struct skl_sst *ctx,
391 struct skl_module_cfg *mconfig)
392{
393 u16 param_size;
394
395 switch (mconfig->m_type) {
396 case SKL_MODULE_TYPE_COPIER:
397 param_size = sizeof(struct skl_cpr_cfg);
398 param_size += mconfig->formats_config.caps_size;
399 return param_size;
400
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530401 case SKL_MODULE_TYPE_SRCINT:
402 return sizeof(struct skl_src_module_cfg);
403
404 case SKL_MODULE_TYPE_UPDWMIX:
405 return sizeof(struct skl_up_down_mixer_cfg);
406
Jeeja KP23db4722015-08-01 19:40:41 +0530407 default:
408 /*
409 * return only base cfg when no specific module type is
410 * specified
411 */
412 return sizeof(struct skl_base_cfg);
413 }
414
415 return 0;
416}
417
418/*
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530419 * DSP firmware supports various modules like copier, SRC, updown etc.
420 * These modules required various parameters to be calculated and sent for
421 * the module initialization to DSP. By default a generic module needs only
422 * base module format configuration
Jeeja KP23db4722015-08-01 19:40:41 +0530423 */
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530424
Jeeja KP23db4722015-08-01 19:40:41 +0530425static int skl_set_module_format(struct skl_sst *ctx,
426 struct skl_module_cfg *module_config,
427 u16 *module_config_size,
428 void **param_data)
429{
430 u16 param_size;
431
432 param_size = skl_get_module_param_size(ctx, module_config);
433
434 *param_data = kzalloc(param_size, GFP_KERNEL);
435 if (NULL == *param_data)
436 return -ENOMEM;
437
438 *module_config_size = param_size;
439
440 switch (module_config->m_type) {
441 case SKL_MODULE_TYPE_COPIER:
442 skl_set_copier_format(ctx, module_config, *param_data);
443 break;
444
Hardik T Shaha0ffe482015-08-01 19:40:42 +0530445 case SKL_MODULE_TYPE_SRCINT:
446 skl_set_src_format(ctx, module_config, *param_data);
447 break;
448
449 case SKL_MODULE_TYPE_UPDWMIX:
450 skl_set_updown_mixer_format(ctx, module_config, *param_data);
451 break;
452
Jeeja KP23db4722015-08-01 19:40:41 +0530453 default:
454 skl_set_base_module_format(ctx, module_config, *param_data);
455 break;
456
457 }
458
459 dev_dbg(ctx->dev, "Module type=%d config size: %d bytes\n",
460 module_config->id.module_id, param_size);
461 print_hex_dump(KERN_DEBUG, "Module params:", DUMP_PREFIX_OFFSET, 8, 4,
462 *param_data, param_size, false);
463 return 0;
464}
465
466static int skl_get_queue_index(struct skl_module_pin *mpin,
467 struct skl_module_inst_id id, int max)
468{
469 int i;
470
471 for (i = 0; i < max; i++) {
472 if (mpin[i].id.module_id == id.module_id &&
473 mpin[i].id.instance_id == id.instance_id)
474 return i;
475 }
476
477 return -EINVAL;
478}
479
480/*
481 * Allocates queue for each module.
482 * if dynamic, the pin_index is allocated 0 to max_pin.
483 * In static, the pin_index is fixed based on module_id and instance id
484 */
485static int skl_alloc_queue(struct skl_module_pin *mpin,
Jeeja KP4f745702015-10-27 09:22:49 +0900486 struct skl_module_cfg *tgt_cfg, int max)
Jeeja KP23db4722015-08-01 19:40:41 +0530487{
488 int i;
Jeeja KP4f745702015-10-27 09:22:49 +0900489 struct skl_module_inst_id id = tgt_cfg->id;
Jeeja KP23db4722015-08-01 19:40:41 +0530490 /*
491 * if pin in dynamic, find first free pin
492 * otherwise find match module and instance id pin as topology will
493 * ensure a unique pin is assigned to this so no need to
494 * allocate/free
495 */
496 for (i = 0; i < max; i++) {
497 if (mpin[i].is_dynamic) {
Jeeja KP4f745702015-10-27 09:22:49 +0900498 if (!mpin[i].in_use &&
499 mpin[i].pin_state == SKL_PIN_UNBIND) {
500
Jeeja KP23db4722015-08-01 19:40:41 +0530501 mpin[i].in_use = true;
502 mpin[i].id.module_id = id.module_id;
503 mpin[i].id.instance_id = id.instance_id;
Jeeja KP4f745702015-10-27 09:22:49 +0900504 mpin[i].tgt_mcfg = tgt_cfg;
Jeeja KP23db4722015-08-01 19:40:41 +0530505 return i;
506 }
507 } else {
508 if (mpin[i].id.module_id == id.module_id &&
Jeeja KP4f745702015-10-27 09:22:49 +0900509 mpin[i].id.instance_id == id.instance_id &&
510 mpin[i].pin_state == SKL_PIN_UNBIND) {
511
512 mpin[i].tgt_mcfg = tgt_cfg;
Jeeja KP23db4722015-08-01 19:40:41 +0530513 return i;
Jeeja KP4f745702015-10-27 09:22:49 +0900514 }
Jeeja KP23db4722015-08-01 19:40:41 +0530515 }
516 }
517
518 return -EINVAL;
519}
520
521static void skl_free_queue(struct skl_module_pin *mpin, int q_index)
522{
523 if (mpin[q_index].is_dynamic) {
524 mpin[q_index].in_use = false;
525 mpin[q_index].id.module_id = 0;
526 mpin[q_index].id.instance_id = 0;
527 }
Jeeja KP4f745702015-10-27 09:22:49 +0900528 mpin[q_index].pin_state = SKL_PIN_UNBIND;
529 mpin[q_index].tgt_mcfg = NULL;
530}
531
532/* Module state will be set to unint, if all the out pin state is UNBIND */
533
534static void skl_clear_module_state(struct skl_module_pin *mpin, int max,
535 struct skl_module_cfg *mcfg)
536{
537 int i;
538 bool found = false;
539
540 for (i = 0; i < max; i++) {
541 if (mpin[i].pin_state == SKL_PIN_UNBIND)
542 continue;
543 found = true;
544 break;
545 }
546
547 if (!found)
548 mcfg->m_state = SKL_MODULE_UNINIT;
549 return;
Jeeja KP23db4722015-08-01 19:40:41 +0530550}
Jeeja KPbeb73b22015-08-01 19:40:43 +0530551
552/*
553 * A module needs to be instanataited in DSP. A mdoule is present in a
554 * collection of module referred as a PIPE.
555 * We first calculate the module format, based on module type and then
556 * invoke the DSP by sending IPC INIT_INSTANCE using ipc helper
557 */
558int skl_init_module(struct skl_sst *ctx,
Jeeja KP9939a9c2015-11-28 15:01:47 +0530559 struct skl_module_cfg *mconfig)
Jeeja KPbeb73b22015-08-01 19:40:43 +0530560{
561 u16 module_config_size = 0;
562 void *param_data = NULL;
563 int ret;
564 struct skl_ipc_init_instance_msg msg;
565
566 dev_dbg(ctx->dev, "%s: module_id = %d instance=%d\n", __func__,
567 mconfig->id.module_id, mconfig->id.instance_id);
568
569 if (mconfig->pipe->state != SKL_PIPE_CREATED) {
570 dev_err(ctx->dev, "Pipe not created state= %d pipe_id= %d\n",
571 mconfig->pipe->state, mconfig->pipe->ppl_id);
572 return -EIO;
573 }
574
575 ret = skl_set_module_format(ctx, mconfig,
576 &module_config_size, &param_data);
577 if (ret < 0) {
578 dev_err(ctx->dev, "Failed to set module format ret=%d\n", ret);
579 return ret;
580 }
581
582 msg.module_id = mconfig->id.module_id;
583 msg.instance_id = mconfig->id.instance_id;
584 msg.ppl_instance_id = mconfig->pipe->ppl_id;
585 msg.param_data_size = module_config_size;
586 msg.core_id = mconfig->core_id;
587
588 ret = skl_ipc_init_instance(&ctx->ipc, &msg, param_data);
589 if (ret < 0) {
590 dev_err(ctx->dev, "Failed to init instance ret=%d\n", ret);
591 kfree(param_data);
592 return ret;
593 }
594 mconfig->m_state = SKL_MODULE_INIT_DONE;
595
596 return ret;
597}
598
599static void skl_dump_bind_info(struct skl_sst *ctx, struct skl_module_cfg
600 *src_module, struct skl_module_cfg *dst_module)
601{
602 dev_dbg(ctx->dev, "%s: src module_id = %d src_instance=%d\n",
603 __func__, src_module->id.module_id, src_module->id.instance_id);
604 dev_dbg(ctx->dev, "%s: dst_module=%d dst_instacne=%d\n", __func__,
605 dst_module->id.module_id, dst_module->id.instance_id);
606
607 dev_dbg(ctx->dev, "src_module state = %d dst module state = %d\n",
608 src_module->m_state, dst_module->m_state);
609}
610
611/*
612 * On module freeup, we need to unbind the module with modules
613 * it is already bind.
614 * Find the pin allocated and unbind then using bind_unbind IPC
615 */
616int skl_unbind_modules(struct skl_sst *ctx,
617 struct skl_module_cfg *src_mcfg,
618 struct skl_module_cfg *dst_mcfg)
619{
620 int ret;
621 struct skl_ipc_bind_unbind_msg msg;
622 struct skl_module_inst_id src_id = src_mcfg->id;
623 struct skl_module_inst_id dst_id = dst_mcfg->id;
624 int in_max = dst_mcfg->max_in_queue;
625 int out_max = src_mcfg->max_out_queue;
Jeeja KP4f745702015-10-27 09:22:49 +0900626 int src_index, dst_index, src_pin_state, dst_pin_state;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530627
628 skl_dump_bind_info(ctx, src_mcfg, dst_mcfg);
629
Jeeja KPbeb73b22015-08-01 19:40:43 +0530630 /* get src queue index */
631 src_index = skl_get_queue_index(src_mcfg->m_out_pin, dst_id, out_max);
632 if (src_index < 0)
633 return -EINVAL;
634
Jeeja KP4f745702015-10-27 09:22:49 +0900635 msg.src_queue = src_index;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530636
637 /* get dst queue index */
638 dst_index = skl_get_queue_index(dst_mcfg->m_in_pin, src_id, in_max);
639 if (dst_index < 0)
640 return -EINVAL;
641
Jeeja KP4f745702015-10-27 09:22:49 +0900642 msg.dst_queue = dst_index;
643
644 src_pin_state = src_mcfg->m_out_pin[src_index].pin_state;
645 dst_pin_state = dst_mcfg->m_in_pin[dst_index].pin_state;
646
647 if (src_pin_state != SKL_PIN_BIND_DONE ||
648 dst_pin_state != SKL_PIN_BIND_DONE)
649 return 0;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530650
651 msg.module_id = src_mcfg->id.module_id;
652 msg.instance_id = src_mcfg->id.instance_id;
653 msg.dst_module_id = dst_mcfg->id.module_id;
654 msg.dst_instance_id = dst_mcfg->id.instance_id;
655 msg.bind = false;
656
657 ret = skl_ipc_bind_unbind(&ctx->ipc, &msg);
658 if (!ret) {
Jeeja KPbeb73b22015-08-01 19:40:43 +0530659 /* free queue only if unbind is success */
660 skl_free_queue(src_mcfg->m_out_pin, src_index);
661 skl_free_queue(dst_mcfg->m_in_pin, dst_index);
Jeeja KP4f745702015-10-27 09:22:49 +0900662
663 /*
664 * check only if src module bind state, bind is
665 * always from src -> sink
666 */
667 skl_clear_module_state(src_mcfg->m_out_pin, out_max, src_mcfg);
Jeeja KPbeb73b22015-08-01 19:40:43 +0530668 }
669
670 return ret;
671}
672
673/*
674 * Once a module is instantiated it need to be 'bind' with other modules in
675 * the pipeline. For binding we need to find the module pins which are bind
676 * together
677 * This function finds the pins and then sends bund_unbind IPC message to
678 * DSP using IPC helper
679 */
680int skl_bind_modules(struct skl_sst *ctx,
681 struct skl_module_cfg *src_mcfg,
682 struct skl_module_cfg *dst_mcfg)
683{
684 int ret;
685 struct skl_ipc_bind_unbind_msg msg;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530686 int in_max = dst_mcfg->max_in_queue;
687 int out_max = src_mcfg->max_out_queue;
688 int src_index, dst_index;
689
690 skl_dump_bind_info(ctx, src_mcfg, dst_mcfg);
691
692 if (src_mcfg->m_state < SKL_MODULE_INIT_DONE &&
693 dst_mcfg->m_state < SKL_MODULE_INIT_DONE)
694 return 0;
695
Jeeja KP4f745702015-10-27 09:22:49 +0900696 src_index = skl_alloc_queue(src_mcfg->m_out_pin, dst_mcfg, out_max);
Jeeja KPbeb73b22015-08-01 19:40:43 +0530697 if (src_index < 0)
698 return -EINVAL;
699
Jeeja KP4f745702015-10-27 09:22:49 +0900700 msg.src_queue = src_index;
701 dst_index = skl_alloc_queue(dst_mcfg->m_in_pin, src_mcfg, in_max);
Jeeja KPbeb73b22015-08-01 19:40:43 +0530702 if (dst_index < 0) {
703 skl_free_queue(src_mcfg->m_out_pin, src_index);
704 return -EINVAL;
705 }
706
Jeeja KP4f745702015-10-27 09:22:49 +0900707 msg.dst_queue = dst_index;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530708
709 dev_dbg(ctx->dev, "src queue = %d dst queue =%d\n",
710 msg.src_queue, msg.dst_queue);
711
712 msg.module_id = src_mcfg->id.module_id;
713 msg.instance_id = src_mcfg->id.instance_id;
714 msg.dst_module_id = dst_mcfg->id.module_id;
715 msg.dst_instance_id = dst_mcfg->id.instance_id;
716 msg.bind = true;
717
718 ret = skl_ipc_bind_unbind(&ctx->ipc, &msg);
719
720 if (!ret) {
721 src_mcfg->m_state = SKL_MODULE_BIND_DONE;
Jeeja KP4f745702015-10-27 09:22:49 +0900722 src_mcfg->m_out_pin[src_index].pin_state = SKL_PIN_BIND_DONE;
723 dst_mcfg->m_in_pin[dst_index].pin_state = SKL_PIN_BIND_DONE;
Jeeja KPbeb73b22015-08-01 19:40:43 +0530724 } else {
725 /* error case , if IPC fails, clear the queue index */
726 skl_free_queue(src_mcfg->m_out_pin, src_index);
727 skl_free_queue(dst_mcfg->m_in_pin, dst_index);
728 }
729
730 return ret;
731}
Jeeja KPc9b1e832015-08-01 19:40:44 +0530732
733static int skl_set_pipe_state(struct skl_sst *ctx, struct skl_pipe *pipe,
734 enum skl_ipc_pipeline_state state)
735{
736 dev_dbg(ctx->dev, "%s: pipe_satate = %d\n", __func__, state);
737
738 return skl_ipc_set_pipeline_state(&ctx->ipc, pipe->ppl_id, state);
739}
740
741/*
742 * A pipeline is a collection of modules. Before a module in instantiated a
743 * pipeline needs to be created for it.
744 * This function creates pipeline, by sending create pipeline IPC messages
745 * to FW
746 */
747int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe)
748{
749 int ret;
750
751 dev_dbg(ctx->dev, "%s: pipe_id = %d\n", __func__, pipe->ppl_id);
752
753 ret = skl_ipc_create_pipeline(&ctx->ipc, pipe->memory_pages,
754 pipe->pipe_priority, pipe->ppl_id);
755 if (ret < 0) {
756 dev_err(ctx->dev, "Failed to create pipeline\n");
757 return ret;
758 }
759
760 pipe->state = SKL_PIPE_CREATED;
761
762 return 0;
763}
764
765/*
766 * A pipeline needs to be deleted on cleanup. If a pipeline is running, then
767 * pause the pipeline first and then delete it
768 * The pipe delete is done by sending delete pipeline IPC. DSP will stop the
769 * DMA engines and releases resources
770 */
771int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
772{
773 int ret;
774
775 dev_dbg(ctx->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id);
776
777 /* If pipe is not started, do not try to stop the pipe in FW. */
778 if (pipe->state > SKL_PIPE_STARTED) {
779 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
780 if (ret < 0) {
781 dev_err(ctx->dev, "Failed to stop pipeline\n");
782 return ret;
783 }
784
785 pipe->state = SKL_PIPE_PAUSED;
786 } else {
787 /* If pipe was not created in FW, do not try to delete it */
788 if (pipe->state < SKL_PIPE_CREATED)
789 return 0;
790
791 ret = skl_ipc_delete_pipeline(&ctx->ipc, pipe->ppl_id);
792 if (ret < 0)
793 dev_err(ctx->dev, "Failed to delete pipeline\n");
794 }
795
796 return ret;
797}
798
799/*
800 * A pipeline is also a scheduling entity in DSP which can be run, stopped
801 * For processing data the pipe need to be run by sending IPC set pipe state
802 * to DSP
803 */
804int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
805{
806 int ret;
807
808 dev_dbg(ctx->dev, "%s: pipe = %d\n", __func__, pipe->ppl_id);
809
810 /* If pipe was not created in FW, do not try to pause or delete */
811 if (pipe->state < SKL_PIPE_CREATED)
812 return 0;
813
814 /* Pipe has to be paused before it is started */
815 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
816 if (ret < 0) {
817 dev_err(ctx->dev, "Failed to pause pipe\n");
818 return ret;
819 }
820
821 pipe->state = SKL_PIPE_PAUSED;
822
823 ret = skl_set_pipe_state(ctx, pipe, PPL_RUNNING);
824 if (ret < 0) {
825 dev_err(ctx->dev, "Failed to start pipe\n");
826 return ret;
827 }
828
829 pipe->state = SKL_PIPE_STARTED;
830
831 return 0;
832}
833
834/*
835 * Stop the pipeline by sending set pipe state IPC
836 * DSP doesnt implement stop so we always send pause message
837 */
838int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe)
839{
840 int ret;
841
842 dev_dbg(ctx->dev, "In %s pipe=%d\n", __func__, pipe->ppl_id);
843
844 /* If pipe was not created in FW, do not try to pause or delete */
845 if (pipe->state < SKL_PIPE_PAUSED)
846 return 0;
847
848 ret = skl_set_pipe_state(ctx, pipe, PPL_PAUSED);
849 if (ret < 0) {
850 dev_dbg(ctx->dev, "Failed to stop pipe\n");
851 return ret;
852 }
853
854 pipe->state = SKL_PIPE_CREATED;
855
856 return 0;
857}
Jeeja KP9939a9c2015-11-28 15:01:47 +0530858
859/* Algo parameter set helper function */
860int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
861 u32 param_id, struct skl_module_cfg *mcfg)
862{
863 struct skl_ipc_large_config_msg msg;
864
865 msg.module_id = mcfg->id.module_id;
866 msg.instance_id = mcfg->id.instance_id;
867 msg.param_data_size = size;
868 msg.large_param_id = param_id;
869
870 return skl_ipc_set_large_config(&ctx->ipc, &msg, params);
871}