| commit | fd1adef3bff0663c5ac31b45bc4a05fafd43d19b | [log] [tgz] |
|---|---|---|
| author | Koji Matsuoka <koji.matsuoka.xm@renesas.com> | Mon May 16 11:28:15 2016 +0900 |
| committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | Tue Nov 15 01:44:50 2016 +0200 |
| tree | 4e8895caca0db0d50f0551e4c134a6ba1cc99f90 | |
| parent | 9cdced8a39c04cf798ddb2a27cb5952f7d39f633 [diff] |
drm: rcar-du: Fix H/V sync signal polarity configuration The VSL and HSL bits in the DSMR register set the corresponding horizontal and vertical sync signal polarity to active high. The code got it the wrong way around, fix it. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>