| commit | f6a09bace0bb9587985b48ed652f2b292f8de0de | [log] [tgz] |
|---|---|---|
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | Mon Aug 14 19:12:11 2017 +0300 |
| committer | Vineet Gupta <vgupta@synopsys.com> | Fri Sep 01 11:26:25 2017 -0700 |
| tree | 2d6a466f2c83b0ced16455c8291052103309d881 | |
| parent | 9926c29f746d178400543e2056cee4d437e697f3 [diff] |
ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk Add core pll node (core_clk) to manage cpu frequency. core_clk represents pll itself. input_clk represents clock signal source (basically xtal) which comes to pll input. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>