| commit | ece509c10985ba93ccc8c68f808a9e767250041c | [log] [tgz] |
|---|---|---|
| author | Dylan Reid <dgreid@chromium.org> | Mon Nov 03 10:28:56 2014 -0800 |
| committer | Mark Brown <broonie@kernel.org> | Tue Nov 04 19:58:02 2014 +0000 |
| tree | 6d724e9e40fde130752d1f0cd1278e888a27e085 | |
| parent | f114040e3ea6e07372334ade75d1ee0775c355e1 [diff] |
ASoC: max98090: Correct pclk divisor settings The Baytrail-based chromebooks have a 20MHz mclk, the code was setting the divisor incorrectly in this case. According to the 98090 datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20. Correct this and the surrounding clock ranges as well to match the datasheet. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>