| commit | ec97faff743b398e21f74a54c81333f3390093aa | [log] [tgz] |
|---|---|---|
| author | Icenowy Zheng <icenowy@aosc.io> | Fri Jan 03 22:35:03 2020 -0800 |
| committer | Maxime Ripard <maxime@cerno.tech> | Sat Jan 04 09:17:06 2020 +0100 |
| tree | ce53bd2eba2b2b584f3e0845d708717907e28b98 | |
| parent | b406cadbc84d200f9e9b9492c8de6041fe4b0392 [diff] |
clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock
The A64 PLL_CPU clock has the same instability if some factor changed
without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,
H3.
Add the mux and pll notifiers for A64 CPU clock to workaround the
problem.
Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>