| commit | e5cc6aa4b6ef34c3f054af8c61a4f73c157589c3 | [log] [tgz] |
|---|---|---|
| author | Marcin Tomczak <marcin.tomczak@intel.com> | Fri Jan 27 11:14:50 2012 -0800 |
| committer | James Bottomley <JBottomley@Parallels.com> | Sun Feb 19 08:09:00 2012 -0600 |
| tree | 64efa1d1dbece4ce058e7cd19b205bde9ef5bdc1 | |
| parent | e3d338a536330b5ffc9f28d7c6a4cdf6ba51867a [diff] |
[SCSI] isci: enable clock gating Enabling clock gating for power savings on entry to controller ready state. Disable SCU clock gating for power savings on exit from the controller ready state. The gating is fully automated by silicon after setting the mode. Signed-off-by: Marcin Tomczak <marcin.tomczak@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>