| commit | cb98598e68aa6c812d4ee4abb8f69dafecba64bc | [log] [tgz] |
|---|---|---|
| author | Dmitry Osipenko <digetx@gmail.com> | Wed Dec 18 21:44:06 2019 +0300 |
| committer | Thierry Reding <treding@nvidia.com> | Fri Jan 10 15:50:25 2020 +0100 |
| tree | 5449083286a22c9f061a9e36e40836a74266a548 | |
| parent | cf83a28f281fb3cce090e1b99d31b26baef9c13b [diff] |
clk: tegra20/30: Don't pre-initialize displays parent clock Both Tegra20 and Tegra30 are initializing display's parent clock incorrectly because PLLP is running at 216/408MHz while display rate is set to 600MHz, but pre-setting the parent isn't needed at all because display driver selects proper parent anyways. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>