| commit | c7ec75ea4d5316518adc87224e3cff47192579e7 | [log] [tgz] |
|---|---|---|
| author | Dinh Nguyen <dinguyen@kernel.org> | Wed Aug 14 10:30:14 2019 -0500 |
| committer | Stephen Boyd <sboyd@kernel.org> | Wed Aug 14 09:23:21 2019 -0700 |
| tree | cf349df383621c280409c7788127b939ea6b90d8 | |
| parent | baf7b79e1ad79a41fafd8ab8597b9a96962d822d [diff] |
clk: socfpga: stratix10: fix rate caclulationg for cnt_clks Checking bypass_reg is incorrect for calculating the cnt_clk rates. Instead we should be checking that there is a proper hardware register that holds the clock divider. Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>