tree 33bbb14e42e9160f53f5b3b763755575eef25ba4
parent f8fd97521d6381b4a19b1b88692a426a79fe1794
author Sowjanya Komatineni <skomatineni@nvidia.com> 1565984516 -0700
committer Thierry Reding <treding@nvidia.com> 1573480383 +0100

clk: tegra: clk-dfll: Add suspend and resume support

This patch implements DFLL suspend and resume operation.

During system suspend entry, CPU clock will switch CPU to safe
clock source of PLLP and disables DFLL clock output.

DFLL driver suspend confirms DFLL disable state and errors out on
being active.

DFLL is re-initialized during the DFLL driver resume as it goes
through complete reset during suspend entry.

Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>