| commit | a91bb605ec5f93676e503267c89469d02c5b4cbc | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Mon Apr 20 15:13:36 2015 +0200 |
| committer | Thierry Reding <treding@nvidia.com> | Thu Apr 28 12:41:50 2016 +0200 |
| tree | 1f692e3aa61cd951112d17416c3a86570ddbbac0 | |
| parent | eede7113aabd3f40f8d9c32b1690f2859fcb101a [diff] |
clk: tegra: Add sor_safe clock The sor_safe clock is a fixed factor (1:17) clock derived from pll_p. It has a gate bit in the peripheral clock registers. While the SOR is being powered up, sor_safe can be used as the source until the SOR brick can generate its own clock. Signed-off-by: Thierry Reding <treding@nvidia.com>