s3c2410fb: byte ordering fixes
This patch sets correct bits related to the byte ordering of the
framebuffer. This was tested on little endian kernel only. The big endian
kernel may require different settings.
The patch also adds 32 bpp mode which is called 24 bpp by Samsung. One
pixel takes 32 bits but only 24 bits are used in this mode.
Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c
index 108d49e..2ecf771 100644
--- a/drivers/video/s3c2410fb.c
+++ b/drivers/video/s3c2410fb.c
@@ -265,8 +265,8 @@
var->blue.length = 5;
}
break;
- case 24:
- /* 24 bpp 888 */
+ case 32:
+ /* 24 bpp 888 and 8 dummy */
var->red.length = 8;
var->red.offset = 16;
var->green.length = 8;
@@ -274,8 +274,6 @@
var->blue.length = 8;
var->blue.offset = 0;
break;
-
-
}
return 0;
}
@@ -374,11 +372,21 @@
break;
case 8:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
+ regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
+ S3C2410_LCDCON5_FRM565;
+ regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
break;
case 16:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
+ regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
+ regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
break;
-
+ case 32:
+ regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
+ regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
+ S3C2410_LCDCON5_HWSWP |
+ S3C2410_LCDCON5_BPP24BL);
+ break;
default:
/* invalid pixel depth */
dev_err(fbi->dev, "invalid bpp %d\n",
@@ -475,7 +483,9 @@
struct fb_var_screeninfo *var = &info->var;
switch (var->bits_per_pixel) {
+ case 32:
case 16:
+ case 12:
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 1: