| commit | 8b4a7acf7b30c811c5cd8b70b615ca8f9efe86cc | [log] [tgz] |
|---|---|---|
| author | Lukasz Luba <l.luba@partner.samsung.com> | Wed Jun 05 18:54:00 2019 +0200 |
| committer | Sylwester Nawrocki <s.nawrocki@samsung.com> | Thu Jun 06 15:53:10 2019 +0200 |
| tree | 13d6ad8fe81506c804a20622d3622a426a902b69 | |
| parent | cc9bdecf4b8d20b3d3d0f8a6cb3e577548b5539f [diff] |
clk: samsung: add BPLL rate table for Exynos 5422 SoC Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>