tree 6389a50a4347d3613a28caeda3a633f9018d2b1a
parent 9f07925c43b0f082ff39449ebd0f51b38abd23f5
author James Hogan <james.hogan@imgtec.com> 1404468536 +0100
committer Ralf Baechle <ralf@linux-mips.org> 1406930798 +0200

MIPS: perf: Allow for more perf events

In mipsxx_pmu_map_raw_event(), set event_id to base_id after the cpu
type conditional code to allow that code to override the base_id to use
more bits from the config and a higher bit for parity.

This will allow cores with up to 512 events between all even/odd
counters (an 8-bit event id) such as P5600 to use bit 8 for parity.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7243/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>