| commit | 64a1644bc3baa62b769455d811b7999b9a1c6cd1 | [log] [tgz] |
|---|---|---|
| author | Elaine Zhang <zhangqing@rock-chips.com> | Mon Aug 21 16:16:07 2017 +0800 |
| committer | Heiko Stuebner <heiko@sntech.de> | Tue Aug 22 02:55:03 2017 +0200 |
| tree | 45c504a9756f007b43db6793b1dd815608749418 | |
| parent | c7d0045b08a36c2fb7874efc48d747613c6a1ccf [diff] |
clk: rockchip: fix the rv1108 clk_mac sel register description The source clock ordering is wrong, as shown in the TRM: cru_sel24_con[8] rmii_extclk_sel clock source select control register 1'b0: from internal PLL 1'b1: from external IO Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>