| commit | 63256ec5347fb2344a42adbae732b90603c92f35 | [log] [tgz] |
|---|---|---|
| author | Chris Wilson <chris@chris-wilson.co.uk> | Tue Jan 04 18:42:07 2011 +0000 |
| committer | Chris Wilson <chris@chris-wilson.co.uk> | Tue Jan 11 20:42:53 2011 +0000 |
| tree | 5b018e93f38f9e90f3b07beeaac4af08122c5876 | |
| parent | 759010728b1323aec03c5baae13fde8f76e44a99 [diff] |
drm/i915: Enforce write ordering through the GTT We need to ensure that writes through the GTT land before any modification to the MMIO registers and so must impose a mandatory write barrier when flushing the GTT domain. This was revealed by relaxing the write ordering by experimentally mapping the registers and the GATT as write-combining. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>