tree f9ca2fa07862f353af505159e46d3148fbc4bcbd
parent 01ffb1ae84dc1df6fc0c077aad0de597c6ddc05b
author Wolfram Sang <wsa+renesas@sang-engineering.com> 1498663316 +0200
committer Ulf Hansson <ulf.hansson@linaro.org> 1504094486 +0200

mmc: renesas_sdhi_core: on R-Car 2+, make use of CBSY bit

Most registers need to wait until the command is completed, not
necessarily until the bus is free. At least, R-Car 2+ SoCs can signal
that via the CBSY bit, so let's use it there instead of SCLKDIVEN to
save a little bit of delay.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>