| commit | 3e1531dbc333997ae19324993119c42436d3e6b6 | [log] [tgz] |
|---|---|---|
| author | Xing Zheng <zhengxing@rock-chips.com> | Wed Jan 18 12:20:56 2017 +0800 |
| committer | Heiko Stuebner <heiko@sntech.de> | Wed Jan 18 11:23:36 2017 +0100 |
| tree | 31dc140969b600f03204227fa909efb63daadee9 | |
| parent | 1a0abcd634dc3caf0d15cb8625e3f43d77b37031 [diff] |
clk: rockchip: fix the incorrect pclk_edp div width for RK3399 The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. Reported-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Tested-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>