tree 7f0f6b1eb5aa70b6b7f0acfa1991cedd1d8badf8
parent 92c2cc5d5566cb84e4f4a683e73c3516882c2ee8
parent 0d48fc558d01ded71ffad3fe6cca8081847ac9a7
author Kevin Hilman <khilman@baylibre.com> 1491346691 -0700
committer Kevin Hilman <khilman@baylibre.com> 1491346691 -0700

Merge branch 'v4.12/clk-drivers' into v4.12/clk

* v4.12/clk-drivers:
  clk: meson-gxbb: Add GXL/GXM GP0 Variant
  clk: meson-gxbb: Add GP0 PLL init parameters
  clk: meson: Add support for parameters for specific PLLs
  clk: meson-gxbb: Add MALI clocks
  clk: meson: mpll: correct N2 maximum value
  clk: meson8b: add the mplls clocks 0, 1 and 2
  clk: meson: gxbb: mpll: use rw operation
  clk: meson: mpll: add rw operation
  clk: gxbb: put dividers and muxes in tables
  clk: meson8b: put dividers and muxes in tables
  clk: meson: add missing const qualifiers on gate arrays
  clk: meson: fix SET_PARM macro