tree c948172d8bd4687a297837c14d97c04edbd13759
parent 309d673e9596f9706e72615583f2f689cf3fbfb5
author Andrew Jeffery <andrew@aj.id.au> 1570673245 +1030
committer Stephen Boyd <sboyd@kernel.org> 1573231721 -0800

clk: ast2600: Add RMII RCLK gates for all four MACs

RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a
single gate for each MAC.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lkml.kernel.org/r/20191010020725.3990-3-andrew@aj.id.au
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>