| commit | 205577ab6f7ade6185f764ed78fb6875dca40205 | [log] [tgz] |
|---|---|---|
| author | Robin Murphy <robin.murphy@arm.com> | Fri Oct 25 19:08:36 2019 +0100 |
| committer | Will Deacon <will@kernel.org> | Mon Nov 04 19:59:30 2019 +0000 |
| tree | 3dc33876b1194b7d1cf1a384e7216659a6d95344 | |
| parent | 5fb190b0b52552de880536d4f409c4300c25e3d4 [diff] |
iommu/io-pgtable-arm: Rationalise MAIR handling Between VMSAv8-64 and the various 32-bit formats, there is either one 64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers. As such, keeping two 64-bit values in io_pgtable_cfg has always been overkill. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will@kernel.org>