ASoC: Fix FLL reference clock division setup in WM8993
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
diff --git a/sound/soc/codecs/wm8993.c b/sound/soc/codecs/wm8993.c
index f9c49b3..e246ca0 100644
--- a/sound/soc/codecs/wm8993.c
+++ b/sound/soc/codecs/wm8993.c
@@ -345,8 +345,10 @@
/* Fref must be <=13.5MHz */
div = 1;
+ fll_div->fll_clk_ref_div = 0;
while ((Fref / div) > 13500000) {
div *= 2;
+ fll_div->fll_clk_ref_div++;
if (div > 8) {
pr_err("Can't scale %dMHz input down to <=13.5MHz\n",