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review.shift-gmbh.com / SHIFTPHONES / kernel / common / 8d8084d85984b3fa4464c72c4db0a785fb10238f / drivers / clk / sunxi-ng / ccu-sun6i-a31.c
  1. 5682e26 clk: sunxi-ng: a31: Fix CLK_OUT_* clock ops by Chen-Yu Tsai · 7 years ago
  2. ee6501d clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL by Chen-Yu Tsai · 7 years ago
  3. 7f3ed79 clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision by Chen-Yu Tsai · 7 years ago
  4. 1667393 clk: Convert to using %pOF instead of full_name by Rob Herring · 7 years ago
  5. 13e0dde clk: sunxi-ng: Support multiple variable pre-dividers by Chen-Yu Tsai · 8 years ago
  6. 38b8f82 clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset by Chen-Yu Tsai · 8 years ago
  7. 9ad0bb3 clk: sunxi-ng: sun6i: Fix enable bit offset for hdmi-ddc module clock by Chen-Yu Tsai · 8 years ago
  8. 7042125 clk: sunxi-ng: A31: Fix spdif clock register by Marcus Cooper · 8 years ago
  9. 95881a5 clk: sunxi-ng: sun6i-a31: Enable PLL-MIPI LDOs when ungating it by Chen-Yu Tsai · 8 years ago
  10. a17b9e4 clk: sunxi-ng: sun6i-a31: Force AHB1 clock to use PLL6 as parent by Chen-Yu Tsai · 8 years ago
  11. 5254223 clk: sunxi-ng: sun6i-a31: Fix register offset for mipi-csi clk by Chen-Yu Tsai · 8 years ago
  12. d613782 clk: sunxi-ng: sun6i-a31: set CLK_SET_RATE_UNGATE for all PLLs by Chen-Yu Tsai · 8 years ago
  13. d832fdd clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks by Chen-Yu Tsai · 8 years ago
  14. c6e6c96 clk: sunxi-ng: Add A31/A31s clocks by Chen-Yu Tsai · 8 years ago