Thomas Gleixner | 5b497af | 2019-05-29 07:18:09 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 2 | /* |
| 3 | * libnvdimm - Non-volatile-memory Devices Subsystem |
| 4 | * |
| 5 | * Copyright(c) 2013-2015 Intel Corporation. All rights reserved. |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 6 | */ |
| 7 | #ifndef __LIBNVDIMM_H__ |
| 8 | #define __LIBNVDIMM_H__ |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 9 | #include <linux/kernel.h> |
Dan Williams | 62232e45 | 2015-06-08 14:27:06 -0400 | [diff] [blame] | 10 | #include <linux/sizes.h> |
| 11 | #include <linux/types.h> |
Dan Williams | faec6f8 | 2017-06-06 11:10:51 -0700 | [diff] [blame] | 12 | #include <linux/uuid.h> |
Dave Jiang | aa9ad44 | 2017-08-23 12:48:26 -0700 | [diff] [blame] | 13 | #include <linux/spinlock.h> |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 14 | #include <linux/bio.h> |
Dave Jiang | aa9ad44 | 2017-08-23 12:48:26 -0700 | [diff] [blame] | 15 | |
| 16 | struct badrange_entry { |
| 17 | u64 start; |
| 18 | u64 length; |
| 19 | struct list_head list; |
| 20 | }; |
| 21 | |
| 22 | struct badrange { |
| 23 | struct list_head list; |
| 24 | spinlock_t lock; |
| 25 | }; |
Dan Williams | e6dfb2d | 2015-04-25 03:56:17 -0400 | [diff] [blame] | 26 | |
| 27 | enum { |
| 28 | /* when a dimm supports both PMEM and BLK access a label is required */ |
Dan Williams | 8f078b3 | 2017-05-04 14:01:24 -0700 | [diff] [blame] | 29 | NDD_ALIASING = 0, |
Dan Williams | 5813882 | 2015-06-23 20:08:34 -0400 | [diff] [blame] | 30 | /* unarmed memory devices may not persist writes */ |
Dan Williams | 8f078b3 | 2017-05-04 14:01:24 -0700 | [diff] [blame] | 31 | NDD_UNARMED = 1, |
| 32 | /* locked memory devices should not be accessed */ |
| 33 | NDD_LOCKED = 2, |
Dave Jiang | 7d98809 | 2018-12-13 15:36:18 -0700 | [diff] [blame] | 34 | /* memory under security wipes should not be accessed */ |
| 35 | NDD_SECURITY_OVERWRITE = 3, |
| 36 | /* tracking whether or not there is a pending device reference */ |
| 37 | NDD_WORK_PENDING = 4, |
Dan Williams | d5d30d5 | 2019-02-02 16:35:26 -0800 | [diff] [blame] | 38 | /* ignore / filter NSLABEL_FLAG_LOCAL for this DIMM, i.e. no aliasing */ |
| 39 | NDD_NOBLK = 5, |
Dan Williams | 62232e45 | 2015-06-08 14:27:06 -0400 | [diff] [blame] | 40 | |
| 41 | /* need to set a limit somewhere, but yes, this is likely overkill */ |
| 42 | ND_IOCTL_MAX_BUFLEN = SZ_4M, |
Dan Williams | 4577b06 | 2016-02-17 13:08:58 -0800 | [diff] [blame] | 43 | ND_CMD_MAX_ELEM = 5, |
Jerry Hoemann | 40abf9b | 2016-04-11 15:02:28 -0700 | [diff] [blame] | 44 | ND_CMD_MAX_ENVELOPE = 256, |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 45 | ND_MAX_MAPPINGS = 32, |
Dan Williams | 1b40e09 | 2015-05-01 13:34:01 -0400 | [diff] [blame] | 46 | |
Dan Williams | 004f1af | 2015-08-24 19:20:23 -0400 | [diff] [blame] | 47 | /* region flag indicating to direct-map persistent memory by default */ |
| 48 | ND_REGION_PAGEMAP = 0, |
Dave Jiang | 06e8ccd | 2018-01-31 12:45:38 -0700 | [diff] [blame] | 49 | /* |
| 50 | * Platform ensures entire CPU store data path is flushed to pmem on |
| 51 | * system power loss. |
| 52 | */ |
| 53 | ND_REGION_PERSIST_CACHE = 1, |
Dave Jiang | 30e6d7b | 2018-01-31 12:45:43 -0700 | [diff] [blame] | 54 | /* |
| 55 | * Platform provides mechanisms to automatically flush outstanding |
| 56 | * write data from memory controler to pmem on system power loss. |
| 57 | * (ADR) |
| 58 | */ |
| 59 | ND_REGION_PERSIST_MEMCTRL = 2, |
Dan Williams | 004f1af | 2015-08-24 19:20:23 -0400 | [diff] [blame] | 60 | |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 61 | /* Platform provides asynchronous flush mechanism */ |
| 62 | ND_REGION_ASYNC = 3, |
| 63 | |
Dan Williams | 1b40e09 | 2015-05-01 13:34:01 -0400 | [diff] [blame] | 64 | /* mark newly adjusted resources as requiring a label update */ |
| 65 | DPA_RESOURCE_ADJUSTED = 1 << 0, |
Dan Williams | e6dfb2d | 2015-04-25 03:56:17 -0400 | [diff] [blame] | 66 | }; |
| 67 | |
Dan Williams | 45def22 | 2015-04-26 19:26:48 -0400 | [diff] [blame] | 68 | extern struct attribute_group nvdimm_bus_attribute_group; |
Dan Williams | 62232e45 | 2015-06-08 14:27:06 -0400 | [diff] [blame] | 69 | extern struct attribute_group nvdimm_attribute_group; |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 70 | extern struct attribute_group nd_device_attribute_group; |
Toshi Kani | 74ae66c | 2015-06-19 12:18:34 -0600 | [diff] [blame] | 71 | extern struct attribute_group nd_numa_attribute_group; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 72 | extern struct attribute_group nd_region_attribute_group; |
| 73 | extern struct attribute_group nd_mapping_attribute_group; |
Dan Williams | 45def22 | 2015-04-26 19:26:48 -0400 | [diff] [blame] | 74 | |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 75 | struct nvdimm; |
| 76 | struct nvdimm_bus_descriptor; |
| 77 | typedef int (*ndctl_fn)(struct nvdimm_bus_descriptor *nd_desc, |
| 78 | struct nvdimm *nvdimm, unsigned int cmd, void *buf, |
Dan Williams | aef2533 | 2016-02-12 17:01:11 -0800 | [diff] [blame] | 79 | unsigned int buf_len, int *cmd_rc); |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 80 | |
Oliver O'Halloran | 1ff19f4 | 2018-04-06 15:21:13 +1000 | [diff] [blame] | 81 | struct device_node; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 82 | struct nvdimm_bus_descriptor { |
Dan Williams | 45def22 | 2015-04-26 19:26:48 -0400 | [diff] [blame] | 83 | const struct attribute_group **attr_groups; |
Jerry Hoemann | 7db5bb3 | 2017-06-30 20:53:24 -0700 | [diff] [blame] | 84 | unsigned long bus_dsm_mask; |
Dan Williams | e3654ec | 2016-04-28 16:17:07 -0700 | [diff] [blame] | 85 | unsigned long cmd_mask; |
Dan Williams | bc9775d | 2016-07-21 20:03:19 -0700 | [diff] [blame] | 86 | struct module *module; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 87 | char *provider_name; |
Oliver O'Halloran | 1ff19f4 | 2018-04-06 15:21:13 +1000 | [diff] [blame] | 88 | struct device_node *of_node; |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 89 | ndctl_fn ndctl; |
Dan Williams | 7ae0fa43 | 2016-02-19 12:16:34 -0800 | [diff] [blame] | 90 | int (*flush_probe)(struct nvdimm_bus_descriptor *nd_desc); |
Dan Williams | 87bf572 | 2016-02-22 21:50:31 -0800 | [diff] [blame] | 91 | int (*clear_to_send)(struct nvdimm_bus_descriptor *nd_desc, |
Dave Jiang | b3ed2ce | 2018-12-04 10:31:11 -0800 | [diff] [blame] | 92 | struct nvdimm *nvdimm, unsigned int cmd, void *data); |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 93 | }; |
| 94 | |
Dan Williams | 62232e45 | 2015-06-08 14:27:06 -0400 | [diff] [blame] | 95 | struct nd_cmd_desc { |
| 96 | int in_num; |
| 97 | int out_num; |
| 98 | u32 in_sizes[ND_CMD_MAX_ELEM]; |
| 99 | int out_sizes[ND_CMD_MAX_ELEM]; |
| 100 | }; |
| 101 | |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 102 | struct nd_interleave_set { |
Dan Williams | c12c48c | 2017-06-04 10:59:15 +0900 | [diff] [blame] | 103 | /* v1.1 definition of the interleave-set-cookie algorithm */ |
| 104 | u64 cookie1; |
| 105 | /* v1.2 definition of the interleave-set-cookie algorithm */ |
| 106 | u64 cookie2; |
Dan Williams | 86ef58a | 2017-02-28 18:32:48 -0800 | [diff] [blame] | 107 | /* compatibility with initial buggy Linux implementation */ |
| 108 | u64 altcookie; |
Dan Williams | faec6f8 | 2017-06-06 11:10:51 -0700 | [diff] [blame] | 109 | |
| 110 | guid_t type_guid; |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 111 | }; |
| 112 | |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 113 | struct nd_mapping_desc { |
| 114 | struct nvdimm *nvdimm; |
| 115 | u64 start; |
| 116 | u64 size; |
Dan Williams | 401c0a1 | 2017-08-04 17:20:16 -0700 | [diff] [blame] | 117 | int position; |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 118 | }; |
| 119 | |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 120 | struct nd_region; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 121 | struct nd_region_desc { |
| 122 | struct resource *res; |
Dan Williams | 44c462e | 2016-09-19 16:38:50 -0700 | [diff] [blame] | 123 | struct nd_mapping_desc *mapping; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 124 | u16 num_mappings; |
| 125 | const struct attribute_group **attr_groups; |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 126 | struct nd_interleave_set *nd_set; |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 127 | void *provider_data; |
Vishal Verma | 5212e11 | 2015-06-25 04:20:32 -0400 | [diff] [blame] | 128 | int num_lanes; |
Toshi Kani | 41d7a6d | 2015-06-19 12:18:33 -0600 | [diff] [blame] | 129 | int numa_node; |
Dan Williams | 8fc5c73 | 2018-11-09 12:43:07 -0800 | [diff] [blame] | 130 | int target_node; |
Dan Williams | 004f1af | 2015-08-24 19:20:23 -0400 | [diff] [blame] | 131 | unsigned long flags; |
Oliver O'Halloran | 1ff19f4 | 2018-04-06 15:21:13 +1000 | [diff] [blame] | 132 | struct device_node *of_node; |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 133 | int (*flush)(struct nd_region *nd_region, struct bio *bio); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 134 | }; |
| 135 | |
Dan Williams | 29b9aa0 | 2016-06-06 17:42:38 -0700 | [diff] [blame] | 136 | struct device; |
| 137 | void *devm_nvdimm_memremap(struct device *dev, resource_size_t offset, |
| 138 | size_t size, unsigned long flags); |
| 139 | static inline void __iomem *devm_nvdimm_ioremap(struct device *dev, |
| 140 | resource_size_t offset, size_t size) |
| 141 | { |
| 142 | return (void __iomem *) devm_nvdimm_memremap(dev, offset, size, 0); |
| 143 | } |
| 144 | |
Dan Williams | 62232e45 | 2015-06-08 14:27:06 -0400 | [diff] [blame] | 145 | struct nvdimm_bus; |
Dan Williams | 3d88002 | 2015-05-31 15:02:11 -0400 | [diff] [blame] | 146 | struct module; |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 147 | struct device; |
| 148 | struct nd_blk_region; |
| 149 | struct nd_blk_region_desc { |
| 150 | int (*enable)(struct nvdimm_bus *nvdimm_bus, struct device *dev); |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 151 | int (*do_io)(struct nd_blk_region *ndbr, resource_size_t dpa, |
| 152 | void *iobuf, u64 len, int rw); |
| 153 | struct nd_region_desc ndr_desc; |
| 154 | }; |
| 155 | |
| 156 | static inline struct nd_blk_region_desc *to_blk_region_desc( |
| 157 | struct nd_region_desc *ndr_desc) |
| 158 | { |
| 159 | return container_of(ndr_desc, struct nd_blk_region_desc, ndr_desc); |
| 160 | |
| 161 | } |
| 162 | |
Dave Jiang | f298939 | 2018-12-05 23:39:29 -0800 | [diff] [blame] | 163 | enum nvdimm_security_state { |
Dan Williams | 1cb95e0 | 2019-01-08 15:34:52 -0800 | [diff] [blame] | 164 | NVDIMM_SECURITY_ERROR = -1, |
Dave Jiang | f298939 | 2018-12-05 23:39:29 -0800 | [diff] [blame] | 165 | NVDIMM_SECURITY_DISABLED, |
| 166 | NVDIMM_SECURITY_UNLOCKED, |
| 167 | NVDIMM_SECURITY_LOCKED, |
| 168 | NVDIMM_SECURITY_FROZEN, |
| 169 | NVDIMM_SECURITY_OVERWRITE, |
| 170 | }; |
| 171 | |
Dave Jiang | 4c6926a | 2018-12-06 12:40:01 -0800 | [diff] [blame] | 172 | #define NVDIMM_PASSPHRASE_LEN 32 |
| 173 | #define NVDIMM_KEY_DESC_LEN 22 |
| 174 | |
| 175 | struct nvdimm_key_data { |
| 176 | u8 data[NVDIMM_PASSPHRASE_LEN]; |
| 177 | }; |
| 178 | |
Dave Jiang | 89fa9d8 | 2018-12-10 10:53:22 -0700 | [diff] [blame] | 179 | enum nvdimm_passphrase_type { |
| 180 | NVDIMM_USER, |
| 181 | NVDIMM_MASTER, |
| 182 | }; |
| 183 | |
Dave Jiang | f298939 | 2018-12-05 23:39:29 -0800 | [diff] [blame] | 184 | struct nvdimm_security_ops { |
Dave Jiang | 89fa9d8 | 2018-12-10 10:53:22 -0700 | [diff] [blame] | 185 | enum nvdimm_security_state (*state)(struct nvdimm *nvdimm, |
| 186 | enum nvdimm_passphrase_type pass_type); |
Dave Jiang | 37833fb | 2018-12-06 09:14:08 -0800 | [diff] [blame] | 187 | int (*freeze)(struct nvdimm *nvdimm); |
Dave Jiang | 4c6926a | 2018-12-06 12:40:01 -0800 | [diff] [blame] | 188 | int (*change_key)(struct nvdimm *nvdimm, |
| 189 | const struct nvdimm_key_data *old_data, |
Dave Jiang | 89fa9d8 | 2018-12-10 10:53:22 -0700 | [diff] [blame] | 190 | const struct nvdimm_key_data *new_data, |
| 191 | enum nvdimm_passphrase_type pass_type); |
Dave Jiang | 4c6926a | 2018-12-06 12:40:01 -0800 | [diff] [blame] | 192 | int (*unlock)(struct nvdimm *nvdimm, |
| 193 | const struct nvdimm_key_data *key_data); |
Dave Jiang | 03b65b2 | 2018-12-07 10:33:30 -0700 | [diff] [blame] | 194 | int (*disable)(struct nvdimm *nvdimm, |
| 195 | const struct nvdimm_key_data *key_data); |
Dave Jiang | 64e77c8 | 2018-12-07 14:02:12 -0700 | [diff] [blame] | 196 | int (*erase)(struct nvdimm *nvdimm, |
Dave Jiang | 89fa9d8 | 2018-12-10 10:53:22 -0700 | [diff] [blame] | 197 | const struct nvdimm_key_data *key_data, |
| 198 | enum nvdimm_passphrase_type pass_type); |
Dave Jiang | 7d98809 | 2018-12-13 15:36:18 -0700 | [diff] [blame] | 199 | int (*overwrite)(struct nvdimm *nvdimm, |
| 200 | const struct nvdimm_key_data *key_data); |
| 201 | int (*query_overwrite)(struct nvdimm *nvdimm); |
Dave Jiang | f298939 | 2018-12-05 23:39:29 -0800 | [diff] [blame] | 202 | }; |
| 203 | |
Dave Jiang | aa9ad44 | 2017-08-23 12:48:26 -0700 | [diff] [blame] | 204 | void badrange_init(struct badrange *badrange); |
| 205 | int badrange_add(struct badrange *badrange, u64 addr, u64 length); |
| 206 | void badrange_forget(struct badrange *badrange, phys_addr_t start, |
| 207 | unsigned int len); |
| 208 | int nvdimm_bus_add_badrange(struct nvdimm_bus *nvdimm_bus, u64 addr, |
| 209 | u64 length); |
Dan Williams | bc9775d | 2016-07-21 20:03:19 -0700 | [diff] [blame] | 210 | struct nvdimm_bus *nvdimm_bus_register(struct device *parent, |
| 211 | struct nvdimm_bus_descriptor *nfit_desc); |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 212 | void nvdimm_bus_unregister(struct nvdimm_bus *nvdimm_bus); |
Dan Williams | 45def22 | 2015-04-26 19:26:48 -0400 | [diff] [blame] | 213 | struct nvdimm_bus *to_nvdimm_bus(struct device *dev); |
Dave Jiang | f298939 | 2018-12-05 23:39:29 -0800 | [diff] [blame] | 214 | struct nvdimm_bus *nvdimm_to_bus(struct nvdimm *nvdimm); |
Dan Williams | e6dfb2d | 2015-04-25 03:56:17 -0400 | [diff] [blame] | 215 | struct nvdimm *to_nvdimm(struct device *dev); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 216 | struct nd_region *to_nd_region(struct device *dev); |
Dan Williams | 243f29f | 2018-04-02 13:14:25 -0700 | [diff] [blame] | 217 | struct device *nd_region_dev(struct nd_region *nd_region); |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 218 | struct nd_blk_region *to_nd_blk_region(struct device *dev); |
Dan Williams | 45def22 | 2015-04-26 19:26:48 -0400 | [diff] [blame] | 219 | struct nvdimm_bus_descriptor *to_nd_desc(struct nvdimm_bus *nvdimm_bus); |
Vishal Verma | 37b137f | 2016-07-23 21:51:42 -0700 | [diff] [blame] | 220 | struct device *to_nvdimm_bus_dev(struct nvdimm_bus *nvdimm_bus); |
Dan Williams | e6dfb2d | 2015-04-25 03:56:17 -0400 | [diff] [blame] | 221 | const char *nvdimm_name(struct nvdimm *nvdimm); |
Dan Williams | ba9c8dd | 2016-08-22 19:28:37 -0700 | [diff] [blame] | 222 | struct kobject *nvdimm_kobj(struct nvdimm *nvdimm); |
Dan Williams | e3654ec | 2016-04-28 16:17:07 -0700 | [diff] [blame] | 223 | unsigned long nvdimm_cmd_mask(struct nvdimm *nvdimm); |
Dan Williams | e6dfb2d | 2015-04-25 03:56:17 -0400 | [diff] [blame] | 224 | void *nvdimm_provider_data(struct nvdimm *nvdimm); |
Dave Jiang | d6548ae | 2018-12-04 10:31:20 -0800 | [diff] [blame] | 225 | struct nvdimm *__nvdimm_create(struct nvdimm_bus *nvdimm_bus, |
| 226 | void *provider_data, const struct attribute_group **groups, |
| 227 | unsigned long flags, unsigned long cmd_mask, int num_flush, |
Dave Jiang | f298939 | 2018-12-05 23:39:29 -0800 | [diff] [blame] | 228 | struct resource *flush_wpq, const char *dimm_id, |
| 229 | const struct nvdimm_security_ops *sec_ops); |
Dave Jiang | d6548ae | 2018-12-04 10:31:20 -0800 | [diff] [blame] | 230 | static inline struct nvdimm *nvdimm_create(struct nvdimm_bus *nvdimm_bus, |
| 231 | void *provider_data, const struct attribute_group **groups, |
| 232 | unsigned long flags, unsigned long cmd_mask, int num_flush, |
| 233 | struct resource *flush_wpq) |
| 234 | { |
| 235 | return __nvdimm_create(nvdimm_bus, provider_data, groups, flags, |
Dave Jiang | f298939 | 2018-12-05 23:39:29 -0800 | [diff] [blame] | 236 | cmd_mask, num_flush, flush_wpq, NULL, NULL); |
Dave Jiang | d6548ae | 2018-12-04 10:31:20 -0800 | [diff] [blame] | 237 | } |
| 238 | |
Dan Williams | 62232e45 | 2015-06-08 14:27:06 -0400 | [diff] [blame] | 239 | const struct nd_cmd_desc *nd_cmd_dimm_desc(int cmd); |
| 240 | const struct nd_cmd_desc *nd_cmd_bus_desc(int cmd); |
| 241 | u32 nd_cmd_in_size(struct nvdimm *nvdimm, int cmd, |
| 242 | const struct nd_cmd_desc *desc, int idx, void *buf); |
| 243 | u32 nd_cmd_out_size(struct nvdimm *nvdimm, int cmd, |
| 244 | const struct nd_cmd_desc *desc, int idx, const u32 *in_field, |
Dan Williams | efda1b5d | 2016-12-06 09:10:12 -0800 | [diff] [blame] | 245 | const u32 *out_field, unsigned long remainder); |
Dan Williams | 4d88a97 | 2015-05-31 14:41:48 -0400 | [diff] [blame] | 246 | int nvdimm_bus_check_dimm_count(struct nvdimm_bus *nvdimm_bus, int dimm_count); |
Dan Williams | 1f7df6f | 2015-06-09 20:13:14 -0400 | [diff] [blame] | 247 | struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus, |
| 248 | struct nd_region_desc *ndr_desc); |
| 249 | struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus, |
| 250 | struct nd_region_desc *ndr_desc); |
| 251 | struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus, |
| 252 | struct nd_region_desc *ndr_desc); |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 253 | void *nd_region_provider_data(struct nd_region *nd_region); |
| 254 | void *nd_blk_region_provider_data(struct nd_blk_region *ndbr); |
| 255 | void nd_blk_region_set_provider_data(struct nd_blk_region *ndbr, void *data); |
| 256 | struct nvdimm *nd_blk_region_to_dimm(struct nd_blk_region *ndbr); |
Dan Williams | ca6a465 | 2017-01-13 20:36:58 -0800 | [diff] [blame] | 257 | unsigned long nd_blk_memremap_flags(struct nd_blk_region *ndbr); |
Ross Zwisler | 047fc8a | 2015-06-25 04:21:02 -0400 | [diff] [blame] | 258 | unsigned int nd_region_acquire_lane(struct nd_region *nd_region); |
| 259 | void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane); |
Dan Williams | eaf9615 | 2015-05-01 13:11:27 -0400 | [diff] [blame] | 260 | u64 nd_fletcher64(void *addr, size_t len, bool le); |
Pankaj Gupta | c5d4355 | 2019-07-05 19:33:22 +0530 | [diff] [blame] | 261 | int nvdimm_flush(struct nd_region *nd_region, struct bio *bio); |
| 262 | int generic_nvdimm_flush(struct nd_region *nd_region); |
Dan Williams | f284a4f | 2016-07-07 19:44:50 -0700 | [diff] [blame] | 263 | int nvdimm_has_flush(struct nd_region *nd_region); |
Dan Williams | 0b27796 | 2017-06-09 09:46:50 -0700 | [diff] [blame] | 264 | int nvdimm_has_cache(struct nd_region *nd_region); |
Dave Jiang | 7d98809 | 2018-12-13 15:36:18 -0700 | [diff] [blame] | 265 | int nvdimm_in_overwrite(struct nvdimm *nvdimm); |
Robin Murphy | 5deb67f | 2017-08-31 12:27:09 +0100 | [diff] [blame] | 266 | |
Dave Jiang | f298939 | 2018-12-05 23:39:29 -0800 | [diff] [blame] | 267 | static inline int nvdimm_ctl(struct nvdimm *nvdimm, unsigned int cmd, void *buf, |
| 268 | unsigned int buf_len, int *cmd_rc) |
| 269 | { |
| 270 | struct nvdimm_bus *nvdimm_bus = nvdimm_to_bus(nvdimm); |
| 271 | struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus); |
| 272 | |
| 273 | return nd_desc->ndctl(nd_desc, nvdimm, cmd, buf, buf_len, cmd_rc); |
| 274 | } |
| 275 | |
Robin Murphy | 5deb67f | 2017-08-31 12:27:09 +0100 | [diff] [blame] | 276 | #ifdef CONFIG_ARCH_HAS_PMEM_API |
| 277 | #define ARCH_MEMREMAP_PMEM MEMREMAP_WB |
| 278 | void arch_wb_cache_pmem(void *addr, size_t size); |
| 279 | void arch_invalidate_pmem(void *addr, size_t size); |
| 280 | #else |
| 281 | #define ARCH_MEMREMAP_PMEM MEMREMAP_WT |
| 282 | static inline void arch_wb_cache_pmem(void *addr, size_t size) |
| 283 | { |
| 284 | } |
| 285 | static inline void arch_invalidate_pmem(void *addr, size_t size) |
| 286 | { |
| 287 | } |
| 288 | #endif |
| 289 | |
Dan Williams | b94d523 | 2015-05-19 22:54:31 -0400 | [diff] [blame] | 290 | #endif /* __LIBNVDIMM_H__ */ |