Gitiles
Code Review Sign In
review.shift-gmbh.com / SHIFTPHONES / kernel / common / 50d5c60634673a79f8d88564e10345b50fca7378 / . / drivers / scsi / mpt2sas / mpi / mpi2_ioc.h
blob: ea51ce8686908d28053136e4e1b6eb4f02924a8f [file] [log] [blame]
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1/*
2 * Copyright (c) 2000-2009 LSI Corporation.
3 *
4 *
5 * Name: mpi2_ioc.h
6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
7 * Creation Date: October 11, 2006
8 *
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]9 * mpi2_ioc.h Version: 02.00.12
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
18 * MaxTargets.
19 * Added TotalImageSize field to FWDownload Request.
20 * Added reserved words to FWUpload Request.
21 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
22 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
23 * request and replaced it with
24 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
25 * Replaced the MinReplyQueueDepth field of the IOCFacts
26 * reply with MaxReplyDescriptorPostQueueDepth.
27 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
28 * depth for the Reply Descriptor Post Queue.
29 * Added SASAddress field to Initiator Device Table
30 * Overflow Event data.
31 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
32 * for SAS Initiator Device Status Change Event data.
33 * Modified Reason Code defines for SAS Topology Change
34 * List Event data, including adding a bit for PHY Vacant
35 * status, and adding a mask for the Reason Code.
36 * Added define for
37 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
38 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
39 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
40 * the IOCFacts Reply.
41 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
42 * Moved MPI2_VERSION_UNION to mpi2.h.
43 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
44 * instead of enables, and added SASBroadcastPrimitiveMasks
45 * field.
46 * Added Log Entry Added Event and related structure.
47 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
48 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
49 * Added MaxVolumes and MaxPersistentEntries fields to
50 * IOCFacts reply.
51 * Added ProtocalFlags and IOCCapabilities fields to
52 * MPI2_FW_IMAGE_HEADER.
53 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
54 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
55 * a U16 (from a U32).
56 * Removed extra 's' from EventMasks name.
57 * 06-27-08 02.00.08 Fixed an offset in a comment.
58 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
59 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
60 * renamed MinReplyFrameSize to ReplyFrameSize.
61 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
62 * Added two new RAIDOperation values for Integrated RAID
63 * Operations Status Event data.
64 * Added four new IR Configuration Change List Event data
65 * ReasonCode values.
66 * Added two new ReasonCode defines for SAS Device Status
67 * Change Event data.
68 * Added three new DiscoveryStatus bits for the SAS
69 * Discovery event data.
70 * Added Multiplexing Status Change bit to the PhyStatus
71 * field of the SAS Topology Change List event data.
72 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
73 * BootFlags are now product-specific.
74 * Added defines for the indivdual signature bytes
75 * for MPI2_INIT_IMAGE_FOOTER.
76 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
77 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
78 * define.
79 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
80 * define.
81 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]82 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
83 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
84 * Added two new reason codes for SAS Device Status Change
85 * Event.
86 * Added new event: SAS PHY Counter.
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]87 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
88 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
89 * Added new product id family for 2208.
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]90 * --------------------------------------------------------------------------
91 */
92
93#ifndef MPI2_IOC_H
94#define MPI2_IOC_H
95
96/*****************************************************************************
97*
98* IOC Messages
99*
100*****************************************************************************/
101
102/****************************************************************************
103* IOCInit message
104****************************************************************************/
105
106/* IOCInit Request message */
107typedef struct _MPI2_IOC_INIT_REQUEST
108{
109 U8 WhoInit; /* 0x00 */
110 U8 Reserved1; /* 0x01 */
111 U8 ChainOffset; /* 0x02 */
112 U8 Function; /* 0x03 */
113 U16 Reserved2; /* 0x04 */
114 U8 Reserved3; /* 0x06 */
115 U8 MsgFlags; /* 0x07 */
116 U8 VP_ID; /* 0x08 */
117 U8 VF_ID; /* 0x09 */
118 U16 Reserved4; /* 0x0A */
119 U16 MsgVersion; /* 0x0C */
120 U16 HeaderVersion; /* 0x0E */
121 U32 Reserved5; /* 0x10 */
122 U32 Reserved6; /* 0x14 */
123 U16 Reserved7; /* 0x18 */
124 U16 SystemRequestFrameSize; /* 0x1A */
125 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
126 U16 ReplyFreeQueueDepth; /* 0x1E */
127 U32 SenseBufferAddressHigh; /* 0x20 */
128 U32 SystemReplyAddressHigh; /* 0x24 */
129 U64 SystemRequestFrameBaseAddress; /* 0x28 */
130 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
131 U64 ReplyFreeQueueAddress; /* 0x38 */
132 U64 TimeStamp; /* 0x40 */
133} MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
134 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
135
136/* WhoInit values */
137#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
138#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
139#define MPI2_WHOINIT_ROM_BIOS (0x02)
140#define MPI2_WHOINIT_PCI_PEER (0x03)
141#define MPI2_WHOINIT_HOST_DRIVER (0x04)
142#define MPI2_WHOINIT_MANUFACTURER (0x05)
143
144/* MsgVersion */
145#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
146#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
147#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
148#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
149
150/* HeaderVersion */
151#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
152#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
153#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
154#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
155
156/* minimum depth for the Reply Descriptor Post Queue */
157#define MPI2_RDPQ_DEPTH_MIN (16)
158
159
160/* IOCInit Reply message */
161typedef struct _MPI2_IOC_INIT_REPLY
162{
163 U8 WhoInit; /* 0x00 */
164 U8 Reserved1; /* 0x01 */
165 U8 MsgLength; /* 0x02 */
166 U8 Function; /* 0x03 */
167 U16 Reserved2; /* 0x04 */
168 U8 Reserved3; /* 0x06 */
169 U8 MsgFlags; /* 0x07 */
170 U8 VP_ID; /* 0x08 */
171 U8 VF_ID; /* 0x09 */
172 U16 Reserved4; /* 0x0A */
173 U16 Reserved5; /* 0x0C */
174 U16 IOCStatus; /* 0x0E */
175 U32 IOCLogInfo; /* 0x10 */
176} MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
177 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
178
179
180/****************************************************************************
181* IOCFacts message
182****************************************************************************/
183
184/* IOCFacts Request message */
185typedef struct _MPI2_IOC_FACTS_REQUEST
186{
187 U16 Reserved1; /* 0x00 */
188 U8 ChainOffset; /* 0x02 */
189 U8 Function; /* 0x03 */
190 U16 Reserved2; /* 0x04 */
191 U8 Reserved3; /* 0x06 */
192 U8 MsgFlags; /* 0x07 */
193 U8 VP_ID; /* 0x08 */
194 U8 VF_ID; /* 0x09 */
195 U16 Reserved4; /* 0x0A */
196} MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
197 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
198
199
200/* IOCFacts Reply message */
201typedef struct _MPI2_IOC_FACTS_REPLY
202{
203 U16 MsgVersion; /* 0x00 */
204 U8 MsgLength; /* 0x02 */
205 U8 Function; /* 0x03 */
206 U16 HeaderVersion; /* 0x04 */
207 U8 IOCNumber; /* 0x06 */
208 U8 MsgFlags; /* 0x07 */
209 U8 VP_ID; /* 0x08 */
210 U8 VF_ID; /* 0x09 */
211 U16 Reserved1; /* 0x0A */
212 U16 IOCExceptions; /* 0x0C */
213 U16 IOCStatus; /* 0x0E */
214 U32 IOCLogInfo; /* 0x10 */
215 U8 MaxChainDepth; /* 0x14 */
216 U8 WhoInit; /* 0x15 */
217 U8 NumberOfPorts; /* 0x16 */
218 U8 Reserved2; /* 0x17 */
219 U16 RequestCredit; /* 0x18 */
220 U16 ProductID; /* 0x1A */
221 U32 IOCCapabilities; /* 0x1C */
222 MPI2_VERSION_UNION FWVersion; /* 0x20 */
223 U16 IOCRequestFrameSize; /* 0x24 */
224 U16 Reserved3; /* 0x26 */
225 U16 MaxInitiators; /* 0x28 */
226 U16 MaxTargets; /* 0x2A */
227 U16 MaxSasExpanders; /* 0x2C */
228 U16 MaxEnclosures; /* 0x2E */
229 U16 ProtocolFlags; /* 0x30 */
230 U16 HighPriorityCredit; /* 0x32 */
231 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
232 U8 ReplyFrameSize; /* 0x36 */
233 U8 MaxVolumes; /* 0x37 */
234 U16 MaxDevHandle; /* 0x38 */
235 U16 MaxPersistentEntries; /* 0x3A */
236 U32 Reserved4; /* 0x3C */
237} MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
238 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
239
240/* MsgVersion */
241#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
242#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
243#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
244#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
245
246/* HeaderVersion */
247#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
248#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
249#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
250#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
251
252/* IOCExceptions */
253#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
254
255#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
256#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
257#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
258#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
259#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
260
261#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
262#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
263#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
264#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
265#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
266
267/* defines for WhoInit field are after the IOCInit Request */
268
269/* ProductID field uses MPI2_FW_HEADER_PID_ */
270
271/* IOCCapabilities */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]272#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
273#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]274#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
275#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
276#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
277#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
278#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
279#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]280#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]281#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
282#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
283#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
284
285/* ProtocolFlags */
286#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
287#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
288
289
290/****************************************************************************
291* PortFacts message
292****************************************************************************/
293
294/* PortFacts Request message */
295typedef struct _MPI2_PORT_FACTS_REQUEST
296{
297 U16 Reserved1; /* 0x00 */
298 U8 ChainOffset; /* 0x02 */
299 U8 Function; /* 0x03 */
300 U16 Reserved2; /* 0x04 */
301 U8 PortNumber; /* 0x06 */
302 U8 MsgFlags; /* 0x07 */
303 U8 VP_ID; /* 0x08 */
304 U8 VF_ID; /* 0x09 */
305 U16 Reserved3; /* 0x0A */
306} MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
307 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
308
309/* PortFacts Reply message */
310typedef struct _MPI2_PORT_FACTS_REPLY
311{
312 U16 Reserved1; /* 0x00 */
313 U8 MsgLength; /* 0x02 */
314 U8 Function; /* 0x03 */
315 U16 Reserved2; /* 0x04 */
316 U8 PortNumber; /* 0x06 */
317 U8 MsgFlags; /* 0x07 */
318 U8 VP_ID; /* 0x08 */
319 U8 VF_ID; /* 0x09 */
320 U16 Reserved3; /* 0x0A */
321 U16 Reserved4; /* 0x0C */
322 U16 IOCStatus; /* 0x0E */
323 U32 IOCLogInfo; /* 0x10 */
324 U8 Reserved5; /* 0x14 */
325 U8 PortType; /* 0x15 */
326 U16 Reserved6; /* 0x16 */
327 U16 MaxPostedCmdBuffers; /* 0x18 */
328 U16 Reserved7; /* 0x1A */
329} MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
330 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
331
332/* PortType values */
333#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
334#define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
335#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
336#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
337#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
338
339
340/****************************************************************************
341* PortEnable message
342****************************************************************************/
343
344/* PortEnable Request message */
345typedef struct _MPI2_PORT_ENABLE_REQUEST
346{
347 U16 Reserved1; /* 0x00 */
348 U8 ChainOffset; /* 0x02 */
349 U8 Function; /* 0x03 */
350 U8 Reserved2; /* 0x04 */
351 U8 PortFlags; /* 0x05 */
352 U8 Reserved3; /* 0x06 */
353 U8 MsgFlags; /* 0x07 */
354 U8 VP_ID; /* 0x08 */
355 U8 VF_ID; /* 0x09 */
356 U16 Reserved4; /* 0x0A */
357} MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
358 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
359
360
361/* PortEnable Reply message */
362typedef struct _MPI2_PORT_ENABLE_REPLY
363{
364 U16 Reserved1; /* 0x00 */
365 U8 MsgLength; /* 0x02 */
366 U8 Function; /* 0x03 */
367 U8 Reserved2; /* 0x04 */
368 U8 PortFlags; /* 0x05 */
369 U8 Reserved3; /* 0x06 */
370 U8 MsgFlags; /* 0x07 */
371 U8 VP_ID; /* 0x08 */
372 U8 VF_ID; /* 0x09 */
373 U16 Reserved4; /* 0x0A */
374 U16 Reserved5; /* 0x0C */
375 U16 IOCStatus; /* 0x0E */
376 U32 IOCLogInfo; /* 0x10 */
377} MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
378 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
379
380
381/****************************************************************************
382* EventNotification message
383****************************************************************************/
384
385/* EventNotification Request message */
386#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
387
388typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
389{
390 U16 Reserved1; /* 0x00 */
391 U8 ChainOffset; /* 0x02 */
392 U8 Function; /* 0x03 */
393 U16 Reserved2; /* 0x04 */
394 U8 Reserved3; /* 0x06 */
395 U8 MsgFlags; /* 0x07 */
396 U8 VP_ID; /* 0x08 */
397 U8 VF_ID; /* 0x09 */
398 U16 Reserved4; /* 0x0A */
399 U32 Reserved5; /* 0x0C */
400 U32 Reserved6; /* 0x10 */
401 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
402 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
403 U16 Reserved7; /* 0x26 */
404 U32 Reserved8; /* 0x28 */
405} MPI2_EVENT_NOTIFICATION_REQUEST,
406 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
407 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
408
409
410/* EventNotification Reply message */
411typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
412{
413 U16 EventDataLength; /* 0x00 */
414 U8 MsgLength; /* 0x02 */
415 U8 Function; /* 0x03 */
416 U16 Reserved1; /* 0x04 */
417 U8 AckRequired; /* 0x06 */
418 U8 MsgFlags; /* 0x07 */
419 U8 VP_ID; /* 0x08 */
420 U8 VF_ID; /* 0x09 */
421 U16 Reserved2; /* 0x0A */
422 U16 Reserved3; /* 0x0C */
423 U16 IOCStatus; /* 0x0E */
424 U32 IOCLogInfo; /* 0x10 */
425 U16 Event; /* 0x14 */
426 U16 Reserved4; /* 0x16 */
427 U32 EventContext; /* 0x18 */
428 U32 EventData[1]; /* 0x1C */
429} MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
430 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
431
432/* AckRequired */
433#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
434#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
435
436/* Event */
437#define MPI2_EVENT_LOG_DATA (0x0001)
438#define MPI2_EVENT_STATE_CHANGE (0x0002)
439#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
440#define MPI2_EVENT_EVENT_CHANGE (0x000A)
441#define MPI2_EVENT_TASK_SET_FULL (0x000E)
442#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
443#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
444#define MPI2_EVENT_SAS_DISCOVERY (0x0016)
445#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
446#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
447#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
448#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
449#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
450#define MPI2_EVENT_IR_VOLUME (0x001E)
451#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
452#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
453#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]454#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]455#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]456
457
458/* Log Entry Added Event data */
459
460/* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
461#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
462
463typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
464{
465 U64 TimeStamp; /* 0x00 */
466 U32 Reserved1; /* 0x08 */
467 U16 LogSequence; /* 0x0C */
468 U16 LogEntryQualifier; /* 0x0E */
469 U8 VP_ID; /* 0x10 */
470 U8 VF_ID; /* 0x11 */
471 U16 Reserved2; /* 0x12 */
472 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
473} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
474 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
475 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
476
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]477/* GPIO Interrupt Event data */
478
479typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
480 U8 GPIONum; /* 0x00 */
481 U8 Reserved1; /* 0x01 */
482 U16 Reserved2; /* 0x02 */
483} MPI2_EVENT_DATA_GPIO_INTERRUPT,
484 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
485 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
486
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]487/* Hard Reset Received Event data */
488
489typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
490{
491 U8 Reserved1; /* 0x00 */
492 U8 Port; /* 0x01 */
493 U16 Reserved2; /* 0x02 */
494} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
495 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
496 Mpi2EventDataHardResetReceived_t,
497 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
498
499/* Task Set Full Event data */
500
501typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
502{
503 U16 DevHandle; /* 0x00 */
504 U16 CurrentDepth; /* 0x02 */
505} MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
506 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
507
508
509/* SAS Device Status Change Event data */
510
511typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
512{
513 U16 TaskTag; /* 0x00 */
514 U8 ReasonCode; /* 0x02 */
515 U8 Reserved1; /* 0x03 */
516 U8 ASC; /* 0x04 */
517 U8 ASCQ; /* 0x05 */
518 U16 DevHandle; /* 0x06 */
519 U32 Reserved2; /* 0x08 */
520 U64 SASAddress; /* 0x0C */
521 U8 LUN[8]; /* 0x14 */
522} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
523 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
524 Mpi2EventDataSasDeviceStatusChange_t,
525 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
526
527/* SAS Device Status Change Event data ReasonCode values */
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]528#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
529#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
530#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
531#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
532#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
533#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
534#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
535#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
536#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
537#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
538#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
539#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
540#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]541
542
543/* Integrated RAID Operation Status Event data */
544
545typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
546{
547 U16 VolDevHandle; /* 0x00 */
548 U16 Reserved1; /* 0x02 */
549 U8 RAIDOperation; /* 0x04 */
550 U8 PercentComplete; /* 0x05 */
551 U16 Reserved2; /* 0x06 */
552 U32 Resereved3; /* 0x08 */
553} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
554 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
555 Mpi2EventDataIrOperationStatus_t,
556 MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
557
558/* Integrated RAID Operation Status Event data RAIDOperation values */
559#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
560#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
561#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
562#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
563#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
564
565
566/* Integrated RAID Volume Event data */
567
568typedef struct _MPI2_EVENT_DATA_IR_VOLUME
569{
570 U16 VolDevHandle; /* 0x00 */
571 U8 ReasonCode; /* 0x02 */
572 U8 Reserved1; /* 0x03 */
573 U32 NewValue; /* 0x04 */
574 U32 PreviousValue; /* 0x08 */
575} MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
576 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
577
578/* Integrated RAID Volume Event data ReasonCode values */
579#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
580#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
581#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
582
583
584/* Integrated RAID Physical Disk Event data */
585
586typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
587{
588 U16 Reserved1; /* 0x00 */
589 U8 ReasonCode; /* 0x02 */
590 U8 PhysDiskNum; /* 0x03 */
591 U16 PhysDiskDevHandle; /* 0x04 */
592 U16 Reserved2; /* 0x06 */
593 U16 Slot; /* 0x08 */
594 U16 EnclosureHandle; /* 0x0A */
595 U32 NewValue; /* 0x0C */
596 U32 PreviousValue; /* 0x10 */
597} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
598 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
599 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
600
601/* Integrated RAID Physical Disk Event data ReasonCode values */
602#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
603#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
604#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
605
606
607/* Integrated RAID Configuration Change List Event data */
608
609/*
610 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
611 * one and check NumElements at runtime.
612 */
613#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
614#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
615#endif
616
617typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
618{
619 U16 ElementFlags; /* 0x00 */
620 U16 VolDevHandle; /* 0x02 */
621 U8 ReasonCode; /* 0x04 */
622 U8 PhysDiskNum; /* 0x05 */
623 U16 PhysDiskDevHandle; /* 0x06 */
624} MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
625 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
626
627/* IR Configuration Change List Event data ElementFlags values */
628#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
629#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
630#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
631#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
632
633/* IR Configuration Change List Event data ReasonCode values */
634#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
635#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
636#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
637#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
638#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
639#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
640#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
641#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
642#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
643
644typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
645{
646 U8 NumElements; /* 0x00 */
647 U8 Reserved1; /* 0x01 */
648 U8 Reserved2; /* 0x02 */
649 U8 ConfigNum; /* 0x03 */
650 U32 Flags; /* 0x04 */
651 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
652} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
653 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
654 Mpi2EventDataIrConfigChangeList_t,
655 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
656
657/* IR Configuration Change List Event data Flags values */
658#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
659
660
661/* SAS Discovery Event data */
662
663typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
664{
665 U8 Flags; /* 0x00 */
666 U8 ReasonCode; /* 0x01 */
667 U8 PhysicalPort; /* 0x02 */
668 U8 Reserved1; /* 0x03 */
669 U32 DiscoveryStatus; /* 0x04 */
670} MPI2_EVENT_DATA_SAS_DISCOVERY,
671 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
672 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
673
674/* SAS Discovery Event data Flags values */
675#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
676#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
677
678/* SAS Discovery Event data ReasonCode values */
679#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
680#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
681
682/* SAS Discovery Event data DiscoveryStatus values */
683#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
684#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
685#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
686#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
687#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
688#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
689#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
690#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
691#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
692#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
693#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
694#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
695#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
696#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
697#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
698#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
699#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
700#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
701#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
702#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
703
704
705/* SAS Broadcast Primitive Event data */
706
707typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
708{
709 U8 PhyNum; /* 0x00 */
710 U8 Port; /* 0x01 */
711 U8 PortWidth; /* 0x02 */
712 U8 Primitive; /* 0x03 */
713} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
714 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
715 Mpi2EventDataSasBroadcastPrimitive_t,
716 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
717
718/* defines for the Primitive field */
719#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
720#define MPI2_EVENT_PRIMITIVE_SES (0x02)
721#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
722#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
723#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
724#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
725#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
726#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
727
728
729/* SAS Initiator Device Status Change Event data */
730
731typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
732{
733 U8 ReasonCode; /* 0x00 */
734 U8 PhysicalPort; /* 0x01 */
735 U16 DevHandle; /* 0x02 */
736 U64 SASAddress; /* 0x04 */
737} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
738 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
739 Mpi2EventDataSasInitDevStatusChange_t,
740 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
741
742/* SAS Initiator Device Status Change event ReasonCode values */
743#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
744#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
745
746
747/* SAS Initiator Device Table Overflow Event data */
748
749typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
750{
751 U16 MaxInit; /* 0x00 */
752 U16 CurrentInit; /* 0x02 */
753 U64 SASAddress; /* 0x04 */
754} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
755 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
756 Mpi2EventDataSasInitTableOverflow_t,
757 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
758
759
760/* SAS Topology Change List Event data */
761
762/*
763 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
764 * one and check NumEntries at runtime.
765 */
766#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
767#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
768#endif
769
770typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
771{
772 U16 AttachedDevHandle; /* 0x00 */
773 U8 LinkRate; /* 0x02 */
774 U8 PhyStatus; /* 0x03 */
775} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
776 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
777
778typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
779{
780 U16 EnclosureHandle; /* 0x00 */
781 U16 ExpanderDevHandle; /* 0x02 */
782 U8 NumPhys; /* 0x04 */
783 U8 Reserved1; /* 0x05 */
784 U16 Reserved2; /* 0x06 */
785 U8 NumEntries; /* 0x08 */
786 U8 StartPhyNum; /* 0x09 */
787 U8 ExpStatus; /* 0x0A */
788 U8 PhysicalPort; /* 0x0B */
789 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
790} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
791 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
792 Mpi2EventDataSasTopologyChangeList_t,
793 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
794
795/* values for the ExpStatus field */
796#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
797#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
798#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
799#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
800
801/* defines for the LinkRate field */
802#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
803#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
804#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
805#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
806
807#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
808#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
809#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
810#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
811#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
812#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
813#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
814#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
815#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
816
817/* values for the PhyStatus field */
818#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
819#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
820/* values for the PhyStatus ReasonCode sub-field */
821#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
822#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
823#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
824#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
825#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
826#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
827
828
829/* SAS Enclosure Device Status Change Event data */
830
831typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
832{
833 U16 EnclosureHandle; /* 0x00 */
834 U8 ReasonCode; /* 0x02 */
835 U8 PhysicalPort; /* 0x03 */
836 U64 EnclosureLogicalID; /* 0x04 */
837 U16 NumSlots; /* 0x0C */
838 U16 StartSlot; /* 0x0E */
839 U32 PhyBits; /* 0x10 */
840} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
841 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
842 Mpi2EventDataSasEnclDevStatusChange_t,
843 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
844
845/* SAS Enclosure Device Status Change event ReasonCode values */
846#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
847#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
848
849
Kashyap, Desai7b936b02009-09-25 11:44:41 +0530[diff] [blame]850/* SAS PHY Counter Event data */
851
852typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
853 U64 TimeStamp; /* 0x00 */
854 U32 Reserved1; /* 0x08 */
855 U8 PhyEventCode; /* 0x0C */
856 U8 PhyNum; /* 0x0D */
857 U16 Reserved2; /* 0x0E */
858 U32 PhyEventInfo; /* 0x10 */
859 U8 CounterType; /* 0x14 */
860 U8 ThresholdWindow; /* 0x15 */
861 U8 TimeUnits; /* 0x16 */
862 U8 Reserved3; /* 0x17 */
863 U32 EventThreshold; /* 0x18 */
864 U16 ThresholdFlags; /* 0x1C */
865 U16 Reserved4; /* 0x1E */
866} MPI2_EVENT_DATA_SAS_PHY_COUNTER,
867 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
868 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
869
870/* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the
871 * PhyEventCode field
872 * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the
873 * CounterType field
874 * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the
875 * TimeUnits field
876 * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the
877 * ThresholdFlags field
878 * */
879
880
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]881/****************************************************************************
882* EventAck message
883****************************************************************************/
884
885/* EventAck Request message */
886typedef struct _MPI2_EVENT_ACK_REQUEST
887{
888 U16 Reserved1; /* 0x00 */
889 U8 ChainOffset; /* 0x02 */
890 U8 Function; /* 0x03 */
891 U16 Reserved2; /* 0x04 */
892 U8 Reserved3; /* 0x06 */
893 U8 MsgFlags; /* 0x07 */
894 U8 VP_ID; /* 0x08 */
895 U8 VF_ID; /* 0x09 */
896 U16 Reserved4; /* 0x0A */
897 U16 Event; /* 0x0C */
898 U16 Reserved5; /* 0x0E */
899 U32 EventContext; /* 0x10 */
900} MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
901 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
902
903
904/* EventAck Reply message */
905typedef struct _MPI2_EVENT_ACK_REPLY
906{
907 U16 Reserved1; /* 0x00 */
908 U8 MsgLength; /* 0x02 */
909 U8 Function; /* 0x03 */
910 U16 Reserved2; /* 0x04 */
911 U8 Reserved3; /* 0x06 */
912 U8 MsgFlags; /* 0x07 */
913 U8 VP_ID; /* 0x08 */
914 U8 VF_ID; /* 0x09 */
915 U16 Reserved4; /* 0x0A */
916 U16 Reserved5; /* 0x0C */
917 U16 IOCStatus; /* 0x0E */
918 U32 IOCLogInfo; /* 0x10 */
919} MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
920 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
921
922
923/****************************************************************************
924* FWDownload message
925****************************************************************************/
926
927/* FWDownload Request message */
928typedef struct _MPI2_FW_DOWNLOAD_REQUEST
929{
930 U8 ImageType; /* 0x00 */
931 U8 Reserved1; /* 0x01 */
932 U8 ChainOffset; /* 0x02 */
933 U8 Function; /* 0x03 */
934 U16 Reserved2; /* 0x04 */
935 U8 Reserved3; /* 0x06 */
936 U8 MsgFlags; /* 0x07 */
937 U8 VP_ID; /* 0x08 */
938 U8 VF_ID; /* 0x09 */
939 U16 Reserved4; /* 0x0A */
940 U32 TotalImageSize; /* 0x0C */
941 U32 Reserved5; /* 0x10 */
942 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
943} MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
944 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
945
946#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
947
948#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
949#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
950#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
951#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
952#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
953#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
954#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
955
956/* FWDownload TransactionContext Element */
957typedef struct _MPI2_FW_DOWNLOAD_TCSGE
958{
959 U8 Reserved1; /* 0x00 */
960 U8 ContextSize; /* 0x01 */
961 U8 DetailsLength; /* 0x02 */
962 U8 Flags; /* 0x03 */
963 U32 Reserved2; /* 0x04 */
964 U32 ImageOffset; /* 0x08 */
965 U32 ImageSize; /* 0x0C */
966} MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
967 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
968
969/* FWDownload Reply message */
970typedef struct _MPI2_FW_DOWNLOAD_REPLY
971{
972 U8 ImageType; /* 0x00 */
973 U8 Reserved1; /* 0x01 */
974 U8 MsgLength; /* 0x02 */
975 U8 Function; /* 0x03 */
976 U16 Reserved2; /* 0x04 */
977 U8 Reserved3; /* 0x06 */
978 U8 MsgFlags; /* 0x07 */
979 U8 VP_ID; /* 0x08 */
980 U8 VF_ID; /* 0x09 */
981 U16 Reserved4; /* 0x0A */
982 U16 Reserved5; /* 0x0C */
983 U16 IOCStatus; /* 0x0E */
984 U32 IOCLogInfo; /* 0x10 */
985} MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
986 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
987
988
989/****************************************************************************
990* FWUpload message
991****************************************************************************/
992
993/* FWUpload Request message */
994typedef struct _MPI2_FW_UPLOAD_REQUEST
995{
996 U8 ImageType; /* 0x00 */
997 U8 Reserved1; /* 0x01 */
998 U8 ChainOffset; /* 0x02 */
999 U8 Function; /* 0x03 */
1000 U16 Reserved2; /* 0x04 */
1001 U8 Reserved3; /* 0x06 */
1002 U8 MsgFlags; /* 0x07 */
1003 U8 VP_ID; /* 0x08 */
1004 U8 VF_ID; /* 0x09 */
1005 U16 Reserved4; /* 0x0A */
1006 U32 Reserved5; /* 0x0C */
1007 U32 Reserved6; /* 0x10 */
1008 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1009} MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1010 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1011
1012#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1013#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1014#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1015#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1016#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1017#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1018#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1019#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1020#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1021#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1022
1023typedef struct _MPI2_FW_UPLOAD_TCSGE
1024{
1025 U8 Reserved1; /* 0x00 */
1026 U8 ContextSize; /* 0x01 */
1027 U8 DetailsLength; /* 0x02 */
1028 U8 Flags; /* 0x03 */
1029 U32 Reserved2; /* 0x04 */
1030 U32 ImageOffset; /* 0x08 */
1031 U32 ImageSize; /* 0x0C */
1032} MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1033 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1034
1035/* FWUpload Reply message */
1036typedef struct _MPI2_FW_UPLOAD_REPLY
1037{
1038 U8 ImageType; /* 0x00 */
1039 U8 Reserved1; /* 0x01 */
1040 U8 MsgLength; /* 0x02 */
1041 U8 Function; /* 0x03 */
1042 U16 Reserved2; /* 0x04 */
1043 U8 Reserved3; /* 0x06 */
1044 U8 MsgFlags; /* 0x07 */
1045 U8 VP_ID; /* 0x08 */
1046 U8 VF_ID; /* 0x09 */
1047 U16 Reserved4; /* 0x0A */
1048 U16 Reserved5; /* 0x0C */
1049 U16 IOCStatus; /* 0x0E */
1050 U32 IOCLogInfo; /* 0x10 */
1051 U32 ActualImageSize; /* 0x14 */
1052} MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1053 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1054
1055
1056/* FW Image Header */
1057typedef struct _MPI2_FW_IMAGE_HEADER
1058{
1059 U32 Signature; /* 0x00 */
1060 U32 Signature0; /* 0x04 */
1061 U32 Signature1; /* 0x08 */
1062 U32 Signature2; /* 0x0C */
1063 MPI2_VERSION_UNION MPIVersion; /* 0x10 */
1064 MPI2_VERSION_UNION FWVersion; /* 0x14 */
1065 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
1066 MPI2_VERSION_UNION PackageVersion; /* 0x1C */
1067 U16 VendorID; /* 0x20 */
1068 U16 ProductID; /* 0x22 */
1069 U16 ProtocolFlags; /* 0x24 */
1070 U16 Reserved26; /* 0x26 */
1071 U32 IOCCapabilities; /* 0x28 */
1072 U32 ImageSize; /* 0x2C */
1073 U32 NextImageHeaderOffset; /* 0x30 */
1074 U32 Checksum; /* 0x34 */
1075 U32 Reserved38; /* 0x38 */
1076 U32 Reserved3C; /* 0x3C */
1077 U32 Reserved40; /* 0x40 */
1078 U32 Reserved44; /* 0x44 */
1079 U32 Reserved48; /* 0x48 */
1080 U32 Reserved4C; /* 0x4C */
1081 U32 Reserved50; /* 0x50 */
1082 U32 Reserved54; /* 0x54 */
1083 U32 Reserved58; /* 0x58 */
1084 U32 Reserved5C; /* 0x5C */
1085 U32 Reserved60; /* 0x60 */
1086 U32 FirmwareVersionNameWhat; /* 0x64 */
1087 U8 FirmwareVersionName[32]; /* 0x68 */
1088 U32 VendorNameWhat; /* 0x88 */
1089 U8 VendorName[32]; /* 0x8C */
1090 U32 PackageNameWhat; /* 0x88 */
1091 U8 PackageName[32]; /* 0x8C */
1092 U32 ReservedD0; /* 0xD0 */
1093 U32 ReservedD4; /* 0xD4 */
1094 U32 ReservedD8; /* 0xD8 */
1095 U32 ReservedDC; /* 0xDC */
1096 U32 ReservedE0; /* 0xE0 */
1097 U32 ReservedE4; /* 0xE4 */
1098 U32 ReservedE8; /* 0xE8 */
1099 U32 ReservedEC; /* 0xEC */
1100 U32 ReservedF0; /* 0xF0 */
1101 U32 ReservedF4; /* 0xF4 */
1102 U32 ReservedF8; /* 0xF8 */
1103 U32 ReservedFC; /* 0xFC */
1104} MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1105 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1106
1107/* Signature field */
1108#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1109#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1110#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1111
1112/* Signature0 field */
1113#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1114#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1115
1116/* Signature1 field */
1117#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1118#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1119
1120/* Signature2 field */
1121#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1122#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1123
1124
1125/* defines for using the ProductID field */
1126#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1127#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1128
1129#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1130#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1131
1132#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1133/* SAS */
1134#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0010)
Kashyap, Desai9fec5f92009-09-23 17:26:20 +0530[diff] [blame]1135#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0011)
Eric Moore635374e2009-03-09 01:21:12 -0600[diff] [blame]1136
1137/* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1138
1139/* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1140
1141
1142#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1143#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1144#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1145
1146#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1147
1148#define MPI2_FW_HEADER_SIZE (0x100)
1149
1150
1151/* Extended Image Header */
1152typedef struct _MPI2_EXT_IMAGE_HEADER
1153
1154{
1155 U8 ImageType; /* 0x00 */
1156 U8 Reserved1; /* 0x01 */
1157 U16 Reserved2; /* 0x02 */
1158 U32 Checksum; /* 0x04 */
1159 U32 ImageSize; /* 0x08 */
1160 U32 NextImageHeaderOffset; /* 0x0C */
1161 U32 PackageVersion; /* 0x10 */
1162 U32 Reserved3; /* 0x14 */
1163 U32 Reserved4; /* 0x18 */
1164 U32 Reserved5; /* 0x1C */
1165 U8 IdentifyString[32]; /* 0x20 */
1166} MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1167 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1168
1169/* useful offsets */
1170#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1171#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1172#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1173
1174#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1175
1176/* defines for the ImageType field */
1177#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1178#define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1179#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1180#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1181#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1182#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1183#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1184#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1185
1186#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID)
1187
1188
1189
1190/* FLASH Layout Extended Image Data */
1191
1192/*
1193 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1194 * one and check RegionsPerLayout at runtime.
1195 */
1196#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1197#define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1198#endif
1199
1200/*
1201 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1202 * one and check NumberOfLayouts at runtime.
1203 */
1204#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1205#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1206#endif
1207
1208typedef struct _MPI2_FLASH_REGION
1209{
1210 U8 RegionType; /* 0x00 */
1211 U8 Reserved1; /* 0x01 */
1212 U16 Reserved2; /* 0x02 */
1213 U32 RegionOffset; /* 0x04 */
1214 U32 RegionSize; /* 0x08 */
1215 U32 Reserved3; /* 0x0C */
1216} MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1217 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1218
1219typedef struct _MPI2_FLASH_LAYOUT
1220{
1221 U32 FlashSize; /* 0x00 */
1222 U32 Reserved1; /* 0x04 */
1223 U32 Reserved2; /* 0x08 */
1224 U32 Reserved3; /* 0x0C */
1225 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1226} MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1227 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1228
1229typedef struct _MPI2_FLASH_LAYOUT_DATA
1230{
1231 U8 ImageRevision; /* 0x00 */
1232 U8 Reserved1; /* 0x01 */
1233 U8 SizeOfRegion; /* 0x02 */
1234 U8 Reserved2; /* 0x03 */
1235 U16 NumberOfLayouts; /* 0x04 */
1236 U16 RegionsPerLayout; /* 0x06 */
1237 U16 MinimumSectorAlignment; /* 0x08 */
1238 U16 Reserved3; /* 0x0A */
1239 U32 Reserved4; /* 0x0C */
1240 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1241} MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1242 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1243
1244/* defines for the RegionType field */
1245#define MPI2_FLASH_REGION_UNUSED (0x00)
1246#define MPI2_FLASH_REGION_FIRMWARE (0x01)
1247#define MPI2_FLASH_REGION_BIOS (0x02)
1248#define MPI2_FLASH_REGION_NVDATA (0x03)
1249#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1250#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1251#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1252#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1253#define MPI2_FLASH_REGION_MEGARAID (0x09)
1254#define MPI2_FLASH_REGION_INIT (0x0A)
1255
1256/* ImageRevision */
1257#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1258
1259
1260
1261/* Supported Devices Extended Image Data */
1262
1263/*
1264 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1265 * one and check NumberOfDevices at runtime.
1266 */
1267#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1268#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1269#endif
1270
1271typedef struct _MPI2_SUPPORTED_DEVICE
1272{
1273 U16 DeviceID; /* 0x00 */
1274 U16 VendorID; /* 0x02 */
1275 U16 DeviceIDMask; /* 0x04 */
1276 U16 Reserved1; /* 0x06 */
1277 U8 LowPCIRev; /* 0x08 */
1278 U8 HighPCIRev; /* 0x09 */
1279 U16 Reserved2; /* 0x0A */
1280 U32 Reserved3; /* 0x0C */
1281} MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1282 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1283
1284typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1285{
1286 U8 ImageRevision; /* 0x00 */
1287 U8 Reserved1; /* 0x01 */
1288 U8 NumberOfDevices; /* 0x02 */
1289 U8 Reserved2; /* 0x03 */
1290 U32 Reserved3; /* 0x04 */
1291 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1292} MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1293 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1294
1295/* ImageRevision */
1296#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1297
1298
1299/* Init Extended Image Data */
1300
1301typedef struct _MPI2_INIT_IMAGE_FOOTER
1302
1303{
1304 U32 BootFlags; /* 0x00 */
1305 U32 ImageSize; /* 0x04 */
1306 U32 Signature0; /* 0x08 */
1307 U32 Signature1; /* 0x0C */
1308 U32 Signature2; /* 0x10 */
1309 U32 ResetVector; /* 0x14 */
1310} MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1311 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1312
1313/* defines for the BootFlags field */
1314#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1315
1316/* defines for the ImageSize field */
1317#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1318
1319/* defines for the Signature0 field */
1320#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1321#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1322
1323/* defines for the Signature1 field */
1324#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1325#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1326
1327/* defines for the Signature2 field */
1328#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1329#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1330
1331/* Signature fields as individual bytes */
1332#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1333#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1334#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1335#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1336
1337#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1338#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1339#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1340#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1341
1342#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1343#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1344#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1345#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1346
1347/* defines for the ResetVector field */
1348#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1349
1350
1351#endif
1352