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Jeeja KPa40e6932015-07-09 15:20:08 +05301/*
2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
19 *
20 */
21
22#include <linux/pci.h>
23#include <linux/pm_runtime.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include "skl.h"
Jeeja KPb663a8c2015-10-07 11:31:57 +010027#include "skl-topology.h"
Dharageswari.R721c3e32015-12-18 15:12:04 +053028#include "skl-sst-dsp.h"
29#include "skl-sst-ipc.h"
Jeeja KPa40e6932015-07-09 15:20:08 +053030
31#define HDA_MONO 1
32#define HDA_STEREO 2
Jeeja KP8f35bf32015-11-28 15:01:46 +053033#define HDA_QUAD 4
Jeeja KPa40e6932015-07-09 15:20:08 +053034
35static struct snd_pcm_hardware azx_pcm_hw = {
36 .info = (SNDRV_PCM_INFO_MMAP |
37 SNDRV_PCM_INFO_INTERLEAVED |
38 SNDRV_PCM_INFO_BLOCK_TRANSFER |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_PAUSE |
Jeeja KP36379762015-12-18 15:12:09 +053041 SNDRV_PCM_INFO_RESUME |
Jeeja KPa40e6932015-07-09 15:20:08 +053042 SNDRV_PCM_INFO_SYNC_START |
43 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
44 SNDRV_PCM_INFO_HAS_LINK_ATIME |
45 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
Jeeja KP06b23d92015-11-23 22:26:26 +053046 .formats = SNDRV_PCM_FMTBIT_S16_LE |
47 SNDRV_PCM_FMTBIT_S32_LE |
48 SNDRV_PCM_FMTBIT_S24_LE,
49 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
50 SNDRV_PCM_RATE_8000,
51 .rate_min = 8000,
Jeeja KPa40e6932015-07-09 15:20:08 +053052 .rate_max = 48000,
Jeeja KP8f35bf32015-11-28 15:01:46 +053053 .channels_min = 1,
54 .channels_max = HDA_QUAD,
Jeeja KPa40e6932015-07-09 15:20:08 +053055 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
56 .period_bytes_min = 128,
57 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
58 .periods_min = 2,
59 .periods_max = AZX_MAX_FRAG,
60 .fifo_size = 0,
61};
62
63static inline
64struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
65{
66 return substream->runtime->private_data;
67}
68
69static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
70{
71 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
72 struct hdac_stream *hstream = hdac_stream(stream);
73 struct hdac_bus *bus = hstream->bus;
74
75 return hbus_to_ebus(bus);
76}
77
78static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
79 struct snd_pcm_substream *substream,
80 size_t size)
81{
82 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
83
84 hdac_stream(stream)->bufsize = 0;
85 hdac_stream(stream)->period_bytes = 0;
86 hdac_stream(stream)->format_val = 0;
87
88 return snd_pcm_lib_malloc_pages(substream, size);
89}
90
91static int skl_substream_free_pages(struct hdac_bus *bus,
92 struct snd_pcm_substream *substream)
93{
94 return snd_pcm_lib_free_pages(substream);
95}
96
97static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
98 struct snd_pcm_runtime *runtime)
99{
100 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
101
102 /* avoid wrap-around with wall-clock */
103 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
104 20, 178000000);
105}
106
Jeeja KP05057002015-07-09 15:20:11 +0530107static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
108{
109 if (ebus->ppcap)
110 return HDAC_EXT_STREAM_TYPE_HOST;
111 else
112 return HDAC_EXT_STREAM_TYPE_COUPLED;
113}
114
Jeeja KP4557c302015-12-03 23:30:00 +0530115/*
116 * check if the stream opened is marked as ignore_suspend by machine, if so
117 * then enable suspend_active refcount
118 *
119 * The count supend_active does not need lock as it is used in open/close
120 * and suspend context
121 */
122static void skl_set_suspend_active(struct snd_pcm_substream *substream,
123 struct snd_soc_dai *dai, bool enable)
124{
125 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
126 struct snd_soc_dapm_widget *w;
127 struct skl *skl = ebus_to_skl(ebus);
128
129 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
130 w = dai->playback_widget;
131 else
132 w = dai->capture_widget;
133
134 if (w->ignore_suspend && enable)
135 skl->supend_active++;
136 else if (w->ignore_suspend && !enable)
137 skl->supend_active--;
138}
139
Jeeja KPa40e6932015-07-09 15:20:08 +0530140static int skl_pcm_open(struct snd_pcm_substream *substream,
141 struct snd_soc_dai *dai)
142{
143 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
144 struct hdac_ext_stream *stream;
145 struct snd_pcm_runtime *runtime = substream->runtime;
146 struct skl_dma_params *dma_params;
Jeeja KPa40e6932015-07-09 15:20:08 +0530147
148 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KPa40e6932015-07-09 15:20:08 +0530149
150 stream = snd_hdac_ext_stream_assign(ebus, substream,
Jeeja KP05057002015-07-09 15:20:11 +0530151 skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530152 if (stream == NULL)
153 return -EBUSY;
154
155 skl_set_pcm_constrains(ebus, runtime);
156
157 /*
158 * disable WALLCLOCK timestamps for capture streams
159 * until we figure out how to handle digital inputs
160 */
161 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
162 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
163 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
164 }
165
166 runtime->private_data = stream;
167
168 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
169 if (!dma_params)
170 return -ENOMEM;
171
172 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
173 snd_soc_dai_set_dma_data(dai, substream, dma_params);
174
175 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
176 dma_params->stream_tag);
Jeeja KP4557c302015-12-03 23:30:00 +0530177 skl_set_suspend_active(substream, dai, true);
Jeeja KPa40e6932015-07-09 15:20:08 +0530178 snd_pcm_set_sync(substream);
179
180 return 0;
181}
182
183static int skl_get_format(struct snd_pcm_substream *substream,
184 struct snd_soc_dai *dai)
185{
186 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
187 struct skl_dma_params *dma_params;
Jeeja KP05057002015-07-09 15:20:11 +0530188 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530189 int format_val = 0;
Jeeja KPa40e6932015-07-09 15:20:08 +0530190
Jeeja KP05057002015-07-09 15:20:11 +0530191 if (ebus->ppcap) {
192 struct snd_pcm_runtime *runtime = substream->runtime;
193
194 format_val = snd_hdac_calc_stream_format(runtime->rate,
195 runtime->channels,
196 runtime->format,
197 32, 0);
198 } else {
199 struct snd_soc_dai *codec_dai = rtd->codec_dai;
200
201 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
202 if (dma_params)
203 format_val = dma_params->format;
204 }
Jeeja KPa40e6932015-07-09 15:20:08 +0530205
206 return format_val;
207}
208
Dharageswari.Rc115fa52016-02-05 12:19:07 +0530209static int skl_be_prepare(struct snd_pcm_substream *substream,
210 struct snd_soc_dai *dai)
211{
212 struct skl *skl = get_skl_ctx(dai->dev);
213 struct skl_sst *ctx = skl->skl_sst;
214 struct skl_module_cfg *mconfig;
215
216 if ((dai->playback_active > 1) || (dai->capture_active > 1))
217 return 0;
218
219 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
220 if (mconfig == NULL)
221 return -EINVAL;
222
223 return skl_dsp_set_dma_control(ctx, mconfig);
224}
225
Jeeja KPa40e6932015-07-09 15:20:08 +0530226static int skl_pcm_prepare(struct snd_pcm_substream *substream,
227 struct snd_soc_dai *dai)
228{
229 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
230 unsigned int format_val;
231 int err;
232
233 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KPa40e6932015-07-09 15:20:08 +0530234
235 format_val = skl_get_format(substream, dai);
236 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
237 hdac_stream(stream)->stream_tag, format_val);
238 snd_hdac_stream_reset(hdac_stream(stream));
239
240 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
241 if (err < 0)
242 return err;
243
244 err = snd_hdac_stream_setup(hdac_stream(stream));
245 if (err < 0)
246 return err;
247
248 hdac_stream(stream)->prepared = 1;
249
250 return err;
251}
252
253static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
254 struct snd_pcm_hw_params *params,
255 struct snd_soc_dai *dai)
256{
257 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KP05057002015-07-09 15:20:11 +0530258 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530259 struct snd_pcm_runtime *runtime = substream->runtime;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100260 struct skl_pipe_params p_params = {0};
261 struct skl_module_cfg *m_cfg;
Jeeja KP05057002015-07-09 15:20:11 +0530262 int ret, dma_id;
Jeeja KPa40e6932015-07-09 15:20:08 +0530263
264 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
265 ret = skl_substream_alloc_pages(ebus, substream,
266 params_buffer_bytes(params));
267 if (ret < 0)
268 return ret;
269
270 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
271 runtime->rate, runtime->channels, runtime->format);
272
Jeeja KP05057002015-07-09 15:20:11 +0530273 dma_id = hdac_stream(stream)->stream_tag - 1;
274 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
275
Jeeja KPb663a8c2015-10-07 11:31:57 +0100276 p_params.s_fmt = snd_pcm_format_width(params_format(params));
277 p_params.ch = params_channels(params);
278 p_params.s_freq = params_rate(params);
279 p_params.host_dma_id = dma_id;
280 p_params.stream = substream->stream;
281
282 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
283 if (m_cfg)
284 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
285
Jeeja KPa40e6932015-07-09 15:20:08 +0530286 return 0;
287}
288
289static void skl_pcm_close(struct snd_pcm_substream *substream,
290 struct snd_soc_dai *dai)
291{
292 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KP05057002015-07-09 15:20:11 +0530293 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530294 struct skl_dma_params *dma_params = NULL;
Dharageswari.R721c3e32015-12-18 15:12:04 +0530295 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPa40e6932015-07-09 15:20:08 +0530296
297 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KP05057002015-07-09 15:20:11 +0530298
299 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530300
301 dma_params = snd_soc_dai_get_dma_data(dai, substream);
302 /*
303 * now we should set this to NULL as we are freeing by the
304 * dma_params
305 */
306 snd_soc_dai_set_dma_data(dai, substream, NULL);
Jeeja KP4557c302015-12-03 23:30:00 +0530307 skl_set_suspend_active(substream, dai, false);
Jeeja KPa40e6932015-07-09 15:20:08 +0530308
Dharageswari.R721c3e32015-12-18 15:12:04 +0530309 /*
310 * check if close is for "Reference Pin" and set back the
311 * CGCTL.MISCBDCGE if disabled by driver
312 */
313 if (!strncmp(dai->name, "Reference Pin", 13) &&
314 skl->skl_sst->miscbdcg_disabled) {
315 skl->skl_sst->enable_miscbdcge(dai->dev, true);
316 skl->skl_sst->miscbdcg_disabled = false;
317 }
318
Jeeja KPa40e6932015-07-09 15:20:08 +0530319 kfree(dma_params);
320}
321
322static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
323 struct snd_soc_dai *dai)
324{
325 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
326 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
327
328 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
329
330 snd_hdac_stream_cleanup(hdac_stream(stream));
331 hdac_stream(stream)->prepared = 0;
332
333 return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
334}
335
Jeeja KPb663a8c2015-10-07 11:31:57 +0100336static int skl_be_hw_params(struct snd_pcm_substream *substream,
337 struct snd_pcm_hw_params *params,
338 struct snd_soc_dai *dai)
339{
340 struct skl_pipe_params p_params = {0};
341
342 p_params.s_fmt = snd_pcm_format_width(params_format(params));
343 p_params.ch = params_channels(params);
344 p_params.s_freq = params_rate(params);
345 p_params.stream = substream->stream;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100346
Jeeja KP4bd073f2015-10-27 09:22:45 +0900347 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100348}
349
Jeeja KPd1730c32015-10-27 09:22:53 +0900350static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
351 int cmd)
352{
353 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
354 struct hdac_bus *bus = ebus_to_hbus(ebus);
355 struct hdac_ext_stream *stream;
356 int start;
357 unsigned long cookie;
358 struct hdac_stream *hstr;
359
360 stream = get_hdac_ext_stream(substream);
361 hstr = hdac_stream(stream);
362
363 if (!hstr->prepared)
364 return -EPIPE;
365
366 switch (cmd) {
367 case SNDRV_PCM_TRIGGER_START:
368 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
369 case SNDRV_PCM_TRIGGER_RESUME:
370 start = 1;
371 break;
372
373 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
374 case SNDRV_PCM_TRIGGER_SUSPEND:
375 case SNDRV_PCM_TRIGGER_STOP:
376 start = 0;
377 break;
378
379 default:
380 return -EINVAL;
381 }
382
383 spin_lock_irqsave(&bus->reg_lock, cookie);
384
385 if (start) {
386 snd_hdac_stream_start(hdac_stream(stream), true);
387 snd_hdac_stream_timecounter_init(hstr, 0);
388 } else {
389 snd_hdac_stream_stop(hdac_stream(stream));
390 }
391
392 spin_unlock_irqrestore(&bus->reg_lock, cookie);
393
394 return 0;
395}
396
Jeeja KPb663a8c2015-10-07 11:31:57 +0100397static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
398 struct snd_soc_dai *dai)
399{
400 struct skl *skl = get_skl_ctx(dai->dev);
401 struct skl_sst *ctx = skl->skl_sst;
402 struct skl_module_cfg *mconfig;
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530403 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
404 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KPd1730c32015-10-27 09:22:53 +0900405 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100406
407 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
408 if (!mconfig)
409 return -EIO;
410
411 switch (cmd) {
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530412 case SNDRV_PCM_TRIGGER_RESUME:
413 skl_pcm_prepare(substream, dai);
Jeeja KP748a1d52015-12-18 15:12:07 +0530414 /*
415 * enable DMA Resume enable bit for the stream, set the dpib
416 * & lpib position to resune before starting the DMA
417 */
418 snd_hdac_ext_stream_drsm_enable(ebus, true,
419 hdac_stream(stream)->index);
420 snd_hdac_ext_stream_set_dpibr(ebus, stream, stream->dpib);
421 snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
422
Jeeja KPd1730c32015-10-27 09:22:53 +0900423 case SNDRV_PCM_TRIGGER_START:
Jeeja KPb663a8c2015-10-07 11:31:57 +0100424 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Jeeja KPd1730c32015-10-27 09:22:53 +0900425 /*
426 * Start HOST DMA and Start FE Pipe.This is to make sure that
427 * there are no underrun/overrun in the case when the FE
428 * pipeline is started but there is a delay in starting the
429 * DMA channel on the host.
430 */
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530431 snd_hdac_ext_stream_decouple(ebus, stream, true);
Jeeja KPd1730c32015-10-27 09:22:53 +0900432 ret = skl_decoupled_trigger(substream, cmd);
433 if (ret < 0)
434 return ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100435 return skl_run_pipe(ctx, mconfig->pipe);
Jeeja KPd1730c32015-10-27 09:22:53 +0900436 break;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100437
438 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
439 case SNDRV_PCM_TRIGGER_SUSPEND:
Jeeja KPd1730c32015-10-27 09:22:53 +0900440 case SNDRV_PCM_TRIGGER_STOP:
441 /*
442 * Stop FE Pipe first and stop DMA. This is to make sure that
443 * there are no underrun/overrun in the case if there is a delay
444 * between the two operations.
445 */
446 ret = skl_stop_pipe(ctx, mconfig->pipe);
447 if (ret < 0)
448 return ret;
449
450 ret = skl_decoupled_trigger(substream, cmd);
Jeeja KP748a1d52015-12-18 15:12:07 +0530451 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND) {
452 /* save the dpib and lpib positions */
453 stream->dpib = readl(ebus->bus.remap_addr +
454 AZX_REG_VS_SDXDPIB_XBASE +
455 (AZX_REG_VS_SDXDPIB_XINTERVAL *
456 hdac_stream(stream)->index));
457
458 stream->lpib = snd_hdac_stream_get_pos_lpib(
459 hdac_stream(stream));
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530460 snd_hdac_ext_stream_decouple(ebus, stream, false);
Jeeja KP748a1d52015-12-18 15:12:07 +0530461 }
Jeeja KPd1730c32015-10-27 09:22:53 +0900462 break;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100463
464 default:
Jeeja KPd1730c32015-10-27 09:22:53 +0900465 return -EINVAL;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100466 }
Jeeja KPd1730c32015-10-27 09:22:53 +0900467
468 return 0;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100469}
470
Jeeja KP05057002015-07-09 15:20:11 +0530471static int skl_link_hw_params(struct snd_pcm_substream *substream,
472 struct snd_pcm_hw_params *params,
473 struct snd_soc_dai *dai)
474{
475 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
476 struct hdac_ext_stream *link_dev;
477 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
478 struct skl_dma_params *dma_params;
479 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100480 struct skl_pipe_params p_params = {0};
Jeeja KP05057002015-07-09 15:20:11 +0530481
Jeeja KP05057002015-07-09 15:20:11 +0530482 link_dev = snd_hdac_ext_stream_assign(ebus, substream,
483 HDAC_EXT_STREAM_TYPE_LINK);
484 if (!link_dev)
485 return -EBUSY;
486
487 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
488
489 /* set the stream tag in the codec dai dma params */
490 dma_params = (struct skl_dma_params *)
491 snd_soc_dai_get_dma_data(codec_dai, substream);
492 if (dma_params)
493 dma_params->stream_tag = hdac_stream(link_dev)->stream_tag;
494 snd_soc_dai_set_dma_data(codec_dai, substream, (void *)dma_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100495
496 p_params.s_fmt = snd_pcm_format_width(params_format(params));
497 p_params.ch = params_channels(params);
498 p_params.s_freq = params_rate(params);
499 p_params.stream = substream->stream;
500 p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1;
501
Jeeja KP4bd073f2015-10-27 09:22:45 +0900502 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KP05057002015-07-09 15:20:11 +0530503}
504
505static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
506 struct snd_soc_dai *dai)
507{
508 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
509 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
510 struct hdac_ext_stream *link_dev =
511 snd_soc_dai_get_dma_data(dai, substream);
512 unsigned int format_val = 0;
513 struct skl_dma_params *dma_params;
514 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KP05057002015-07-09 15:20:11 +0530515 struct hdac_ext_link *link;
516
Jeeja KP05057002015-07-09 15:20:11 +0530517 dma_params = (struct skl_dma_params *)
518 snd_soc_dai_get_dma_data(codec_dai, substream);
519 if (dma_params)
520 format_val = dma_params->format;
521 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n",
522 hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name);
523
Jeeja KP05057002015-07-09 15:20:11 +0530524 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
525 if (!link)
526 return -EINVAL;
527
Jeeja KP920982c2015-12-18 15:12:08 +0530528 snd_hdac_ext_bus_link_power_up(link);
529 snd_hdac_ext_link_stream_reset(link_dev);
530
531 snd_hdac_ext_link_stream_setup(link_dev, format_val);
532
Jeeja KP05057002015-07-09 15:20:11 +0530533 snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag);
534 link_dev->link_prepared = 1;
535
536 return 0;
537}
538
539static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
540 int cmd, struct snd_soc_dai *dai)
541{
542 struct hdac_ext_stream *link_dev =
543 snd_soc_dai_get_dma_data(dai, substream);
Jeeja KP920982c2015-12-18 15:12:08 +0530544 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
545 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KP05057002015-07-09 15:20:11 +0530546
547 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
548 switch (cmd) {
Jeeja KP920982c2015-12-18 15:12:08 +0530549 case SNDRV_PCM_TRIGGER_RESUME:
550 skl_link_pcm_prepare(substream, dai);
Jeeja KP05057002015-07-09 15:20:11 +0530551 case SNDRV_PCM_TRIGGER_START:
552 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Jeeja KP920982c2015-12-18 15:12:08 +0530553 snd_hdac_ext_stream_decouple(ebus, stream, true);
Jeeja KP05057002015-07-09 15:20:11 +0530554 snd_hdac_ext_link_stream_start(link_dev);
555 break;
556
557 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
558 case SNDRV_PCM_TRIGGER_SUSPEND:
559 case SNDRV_PCM_TRIGGER_STOP:
560 snd_hdac_ext_link_stream_clear(link_dev);
Jeeja KP920982c2015-12-18 15:12:08 +0530561 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
562 snd_hdac_ext_stream_decouple(ebus, stream, false);
Jeeja KP05057002015-07-09 15:20:11 +0530563 break;
564
565 default:
566 return -EINVAL;
567 }
568 return 0;
569}
570
571static int skl_link_hw_free(struct snd_pcm_substream *substream,
572 struct snd_soc_dai *dai)
573{
574 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
575 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
576 struct hdac_ext_stream *link_dev =
577 snd_soc_dai_get_dma_data(dai, substream);
578 struct hdac_ext_link *link;
579
580 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
581
582 link_dev->link_prepared = 0;
583
584 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
585 if (!link)
586 return -EINVAL;
587
588 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
589 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
590 return 0;
591}
592
Jeeja KPa40e6932015-07-09 15:20:08 +0530593static struct snd_soc_dai_ops skl_pcm_dai_ops = {
594 .startup = skl_pcm_open,
595 .shutdown = skl_pcm_close,
596 .prepare = skl_pcm_prepare,
597 .hw_params = skl_pcm_hw_params,
598 .hw_free = skl_pcm_hw_free,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100599 .trigger = skl_pcm_trigger,
Jeeja KPa40e6932015-07-09 15:20:08 +0530600};
601
Jeeja KP05057002015-07-09 15:20:11 +0530602static struct snd_soc_dai_ops skl_dmic_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100603 .hw_params = skl_be_hw_params,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100604};
605
606static struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100607 .hw_params = skl_be_hw_params,
Dharageswari.Rc115fa52016-02-05 12:19:07 +0530608 .prepare = skl_be_prepare,
Jeeja KP05057002015-07-09 15:20:11 +0530609};
610
611static struct snd_soc_dai_ops skl_link_dai_ops = {
Jeeja KP05057002015-07-09 15:20:11 +0530612 .prepare = skl_link_pcm_prepare,
613 .hw_params = skl_link_hw_params,
614 .hw_free = skl_link_hw_free,
615 .trigger = skl_link_pcm_trigger,
Jeeja KP05057002015-07-09 15:20:11 +0530616};
617
Jeeja KPa40e6932015-07-09 15:20:08 +0530618static struct snd_soc_dai_driver skl_platform_dai[] = {
619{
620 .name = "System Pin",
621 .ops = &skl_pcm_dai_ops,
622 .playback = {
623 .stream_name = "System Playback",
624 .channels_min = HDA_MONO,
625 .channels_max = HDA_STEREO,
626 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
627 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
628 },
629 .capture = {
630 .stream_name = "System Capture",
631 .channels_min = HDA_MONO,
632 .channels_max = HDA_STEREO,
633 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
634 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
635 },
636},
637{
Jeeja KP05057002015-07-09 15:20:11 +0530638 .name = "Reference Pin",
639 .ops = &skl_pcm_dai_ops,
640 .capture = {
641 .stream_name = "Reference Capture",
642 .channels_min = HDA_MONO,
Jeeja KP8f35bf32015-11-28 15:01:46 +0530643 .channels_max = HDA_QUAD,
Jeeja KP05057002015-07-09 15:20:11 +0530644 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
645 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
646 },
647},
648{
Jeeja KPa40e6932015-07-09 15:20:08 +0530649 .name = "Deepbuffer Pin",
650 .ops = &skl_pcm_dai_ops,
651 .playback = {
652 .stream_name = "Deepbuffer Playback",
653 .channels_min = HDA_STEREO,
654 .channels_max = HDA_STEREO,
655 .rates = SNDRV_PCM_RATE_48000,
656 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
657 },
658},
659{
660 .name = "LowLatency Pin",
661 .ops = &skl_pcm_dai_ops,
662 .playback = {
663 .stream_name = "Low Latency Playback",
664 .channels_min = HDA_STEREO,
665 .channels_max = HDA_STEREO,
666 .rates = SNDRV_PCM_RATE_48000,
667 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
668 },
669},
Jeeja KP8f35bf32015-11-28 15:01:46 +0530670{
671 .name = "DMIC Pin",
672 .ops = &skl_pcm_dai_ops,
673 .capture = {
674 .stream_name = "DMIC Capture",
675 .channels_min = HDA_MONO,
676 .channels_max = HDA_QUAD,
677 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
678 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
679 },
680},
681
Jeeja KP05057002015-07-09 15:20:11 +0530682/* BE CPU Dais */
683{
Jeeja KPb663a8c2015-10-07 11:31:57 +0100684 .name = "SSP0 Pin",
685 .ops = &skl_be_ssp_dai_ops,
686 .playback = {
687 .stream_name = "ssp0 Tx",
688 .channels_min = HDA_STEREO,
689 .channels_max = HDA_STEREO,
690 .rates = SNDRV_PCM_RATE_48000,
691 .formats = SNDRV_PCM_FMTBIT_S16_LE,
692 },
693 .capture = {
694 .stream_name = "ssp0 Rx",
695 .channels_min = HDA_STEREO,
696 .channels_max = HDA_STEREO,
697 .rates = SNDRV_PCM_RATE_48000,
698 .formats = SNDRV_PCM_FMTBIT_S16_LE,
699 },
700},
701{
Jeeja KPc80fd4d2015-11-05 22:53:06 +0530702 .name = "SSP1 Pin",
703 .ops = &skl_be_ssp_dai_ops,
704 .playback = {
705 .stream_name = "ssp1 Tx",
706 .channels_min = HDA_STEREO,
707 .channels_max = HDA_STEREO,
708 .rates = SNDRV_PCM_RATE_48000,
709 .formats = SNDRV_PCM_FMTBIT_S16_LE,
710 },
711 .capture = {
712 .stream_name = "ssp1 Rx",
713 .channels_min = HDA_STEREO,
714 .channels_max = HDA_STEREO,
715 .rates = SNDRV_PCM_RATE_48000,
716 .formats = SNDRV_PCM_FMTBIT_S16_LE,
717 },
718},
719{
Jeeja KP05057002015-07-09 15:20:11 +0530720 .name = "iDisp Pin",
721 .ops = &skl_link_dai_ops,
722 .playback = {
723 .stream_name = "iDisp Tx",
724 .channels_min = HDA_STEREO,
725 .channels_max = HDA_STEREO,
726 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
727 .formats = SNDRV_PCM_FMTBIT_S16_LE,
728 },
729},
730{
731 .name = "DMIC01 Pin",
732 .ops = &skl_dmic_dai_ops,
733 .capture = {
734 .stream_name = "DMIC01 Rx",
Jeeja KP8f35bf32015-11-28 15:01:46 +0530735 .channels_min = HDA_MONO,
736 .channels_max = HDA_QUAD,
Jeeja KP05057002015-07-09 15:20:11 +0530737 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
738 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
739 },
740},
741{
Jeeja KP05057002015-07-09 15:20:11 +0530742 .name = "HD-Codec Pin",
743 .ops = &skl_link_dai_ops,
744 .playback = {
745 .stream_name = "HD-Codec Tx",
746 .channels_min = HDA_STEREO,
747 .channels_max = HDA_STEREO,
748 .rates = SNDRV_PCM_RATE_48000,
749 .formats = SNDRV_PCM_FMTBIT_S16_LE,
750 },
751 .capture = {
752 .stream_name = "HD-Codec Rx",
753 .channels_min = HDA_STEREO,
754 .channels_max = HDA_STEREO,
755 .rates = SNDRV_PCM_RATE_48000,
756 .formats = SNDRV_PCM_FMTBIT_S16_LE,
757 },
758},
Jeeja KPa40e6932015-07-09 15:20:08 +0530759};
760
761static int skl_platform_open(struct snd_pcm_substream *substream)
762{
763 struct snd_pcm_runtime *runtime;
764 struct snd_soc_pcm_runtime *rtd = substream->private_data;
765 struct snd_soc_dai_link *dai_link = rtd->dai_link;
766
767 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
768 dai_link->cpu_dai_name);
769
770 runtime = substream->runtime;
771 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
772
773 return 0;
774}
775
Jeeja KPb663a8c2015-10-07 11:31:57 +0100776static int skl_coupled_trigger(struct snd_pcm_substream *substream,
Jeeja KPa40e6932015-07-09 15:20:08 +0530777 int cmd)
778{
779 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
780 struct hdac_bus *bus = ebus_to_hbus(ebus);
781 struct hdac_ext_stream *stream;
782 struct snd_pcm_substream *s;
783 bool start;
784 int sbits = 0;
785 unsigned long cookie;
786 struct hdac_stream *hstr;
787
788 stream = get_hdac_ext_stream(substream);
789 hstr = hdac_stream(stream);
790
791 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
792
793 if (!hstr->prepared)
794 return -EPIPE;
795
796 switch (cmd) {
797 case SNDRV_PCM_TRIGGER_START:
798 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
799 case SNDRV_PCM_TRIGGER_RESUME:
800 start = true;
801 break;
802
803 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
804 case SNDRV_PCM_TRIGGER_SUSPEND:
805 case SNDRV_PCM_TRIGGER_STOP:
806 start = false;
807 break;
808
809 default:
810 return -EINVAL;
811 }
812
813 snd_pcm_group_for_each_entry(s, substream) {
814 if (s->pcm->card != substream->pcm->card)
815 continue;
816 stream = get_hdac_ext_stream(s);
817 sbits |= 1 << hdac_stream(stream)->index;
818 snd_pcm_trigger_done(s, substream);
819 }
820
821 spin_lock_irqsave(&bus->reg_lock, cookie);
822
823 /* first, set SYNC bits of corresponding streams */
824 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
825
826 snd_pcm_group_for_each_entry(s, substream) {
827 if (s->pcm->card != substream->pcm->card)
828 continue;
829 stream = get_hdac_ext_stream(s);
830 if (start)
831 snd_hdac_stream_start(hdac_stream(stream), true);
832 else
833 snd_hdac_stream_stop(hdac_stream(stream));
834 }
835 spin_unlock_irqrestore(&bus->reg_lock, cookie);
836
837 snd_hdac_stream_sync(hstr, start, sbits);
838
839 spin_lock_irqsave(&bus->reg_lock, cookie);
840
841 /* reset SYNC bits */
842 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
843 if (start)
844 snd_hdac_stream_timecounter_init(hstr, sbits);
845 spin_unlock_irqrestore(&bus->reg_lock, cookie);
846
847 return 0;
848}
849
Jeeja KP05057002015-07-09 15:20:11 +0530850static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
851 int cmd)
852{
853 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
854
Jeeja KPd1730c32015-10-27 09:22:53 +0900855 if (!ebus->ppcap)
Jeeja KPb663a8c2015-10-07 11:31:57 +0100856 return skl_coupled_trigger(substream, cmd);
Jeeja KPd1730c32015-10-27 09:22:53 +0900857
858 return 0;
Jeeja KP05057002015-07-09 15:20:11 +0530859}
860
Jeeja KPa40e6932015-07-09 15:20:08 +0530861/* calculate runtime delay from LPIB */
862static int skl_get_delay_from_lpib(struct hdac_ext_bus *ebus,
863 struct hdac_ext_stream *sstream,
864 unsigned int pos)
865{
866 struct hdac_bus *bus = ebus_to_hbus(ebus);
867 struct hdac_stream *hstream = hdac_stream(sstream);
868 struct snd_pcm_substream *substream = hstream->substream;
869 int stream = substream->stream;
870 unsigned int lpib_pos = snd_hdac_stream_get_pos_lpib(hstream);
871 int delay;
872
873 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
874 delay = pos - lpib_pos;
875 else
876 delay = lpib_pos - pos;
877
878 if (delay < 0) {
879 if (delay >= hstream->delay_negative_threshold)
880 delay = 0;
881 else
882 delay += hstream->bufsize;
883 }
Vinod Koul33420d62016-02-05 12:19:04 +0530884
885 if (hstream->bufsize == delay)
886 delay = 0;
Jeeja KPa40e6932015-07-09 15:20:08 +0530887
888 if (delay >= hstream->period_bytes) {
889 dev_info(bus->dev,
890 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
891 delay, hstream->period_bytes);
892 delay = 0;
893 }
894
895 return bytes_to_frames(substream->runtime, delay);
896}
897
898static unsigned int skl_get_position(struct hdac_ext_stream *hstream,
899 int codec_delay)
900{
901 struct hdac_stream *hstr = hdac_stream(hstream);
902 struct snd_pcm_substream *substream = hstr->substream;
Vinod Koulc7b2a442015-10-30 20:34:20 +0530903 struct hdac_ext_bus *ebus;
Jeeja KPa40e6932015-07-09 15:20:08 +0530904 unsigned int pos;
905 int delay;
906
907 /* use the position buffer as default */
908 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
909
910 if (pos >= hdac_stream(hstream)->bufsize)
911 pos = 0;
912
913 if (substream->runtime) {
Vinod Koulc7b2a442015-10-30 20:34:20 +0530914 ebus = get_bus_ctx(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530915 delay = skl_get_delay_from_lpib(ebus, hstream, pos)
916 + codec_delay;
917 substream->runtime->delay += delay;
918 }
919
920 return pos;
921}
922
923static snd_pcm_uframes_t skl_platform_pcm_pointer
924 (struct snd_pcm_substream *substream)
925{
926 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
927
928 return bytes_to_frames(substream->runtime,
929 skl_get_position(hstream, 0));
930}
931
932static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
933 u64 nsec)
934{
935 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
936 struct snd_soc_dai *codec_dai = rtd->codec_dai;
937 u64 codec_frames, codec_nsecs;
938
939 if (!codec_dai->driver->ops->delay)
940 return nsec;
941
942 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
943 codec_nsecs = div_u64(codec_frames * 1000000000LL,
944 substream->runtime->rate);
945
946 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
947 return nsec + codec_nsecs;
948
949 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
950}
951
952static int skl_get_time_info(struct snd_pcm_substream *substream,
953 struct timespec *system_ts, struct timespec *audio_ts,
954 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
955 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
956{
957 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
958 struct hdac_stream *hstr = hdac_stream(sstream);
959 u64 nsec;
960
961 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
962 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
963
964 snd_pcm_gettime(substream->runtime, system_ts);
965
966 nsec = timecounter_read(&hstr->tc);
967 nsec = div_u64(nsec, 3); /* can be optimized */
968 if (audio_tstamp_config->report_delay)
969 nsec = skl_adjust_codec_delay(substream, nsec);
970
971 *audio_ts = ns_to_timespec(nsec);
972
973 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
974 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
975 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
976
977 } else {
978 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
979 }
980
981 return 0;
982}
983
984static struct snd_pcm_ops skl_platform_ops = {
985 .open = skl_platform_open,
986 .ioctl = snd_pcm_lib_ioctl,
987 .trigger = skl_platform_pcm_trigger,
988 .pointer = skl_platform_pcm_pointer,
989 .get_time_info = skl_get_time_info,
990 .mmap = snd_pcm_lib_default_mmap,
991 .page = snd_pcm_sgbuf_ops_page,
992};
993
994static void skl_pcm_free(struct snd_pcm *pcm)
995{
996 snd_pcm_lib_preallocate_free_for_all(pcm);
997}
998
999#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
1000
1001static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
1002{
1003 struct snd_soc_dai *dai = rtd->cpu_dai;
1004 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
1005 struct snd_pcm *pcm = rtd->pcm;
1006 unsigned int size;
1007 int retval = 0;
1008 struct skl *skl = ebus_to_skl(ebus);
1009
1010 if (dai->driver->playback.channels_min ||
1011 dai->driver->capture.channels_min) {
1012 /* buffer pre-allocation */
1013 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1014 if (size > MAX_PREALLOC_SIZE)
1015 size = MAX_PREALLOC_SIZE;
1016 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
1017 SNDRV_DMA_TYPE_DEV_SG,
1018 snd_dma_pci_data(skl->pci),
1019 size, MAX_PREALLOC_SIZE);
1020 if (retval) {
1021 dev_err(dai->dev, "dma buffer allocationf fail\n");
1022 return retval;
1023 }
1024 }
1025
1026 return retval;
1027}
1028
Jeeja KPb663a8c2015-10-07 11:31:57 +01001029static int skl_platform_soc_probe(struct snd_soc_platform *platform)
1030{
1031 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
1032
1033 if (ebus->ppcap)
1034 return skl_tplg_init(platform, ebus);
1035
1036 return 0;
1037}
Jeeja KPa40e6932015-07-09 15:20:08 +05301038static struct snd_soc_platform_driver skl_platform_drv = {
Jeeja KPb663a8c2015-10-07 11:31:57 +01001039 .probe = skl_platform_soc_probe,
Jeeja KPa40e6932015-07-09 15:20:08 +05301040 .ops = &skl_platform_ops,
1041 .pcm_new = skl_pcm_new,
1042 .pcm_free = skl_pcm_free,
1043};
1044
1045static const struct snd_soc_component_driver skl_component = {
1046 .name = "pcm",
1047};
1048
1049int skl_platform_register(struct device *dev)
1050{
1051 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +01001052 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1053 struct skl *skl = ebus_to_skl(ebus);
1054
1055 INIT_LIST_HEAD(&skl->ppl_list);
Jeeja KPa40e6932015-07-09 15:20:08 +05301056
1057 ret = snd_soc_register_platform(dev, &skl_platform_drv);
1058 if (ret) {
1059 dev_err(dev, "soc platform registration failed %d\n", ret);
1060 return ret;
1061 }
1062 ret = snd_soc_register_component(dev, &skl_component,
1063 skl_platform_dai,
1064 ARRAY_SIZE(skl_platform_dai));
1065 if (ret) {
1066 dev_err(dev, "soc component registration failed %d\n", ret);
1067 snd_soc_unregister_platform(dev);
1068 }
1069
1070 return ret;
1071
1072}
1073
1074int skl_platform_unregister(struct device *dev)
1075{
1076 snd_soc_unregister_component(dev);
1077 snd_soc_unregister_platform(dev);
1078 return 0;
1079}