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Shawn Guo9daaf312011-10-17 08:42:17 +08001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +080013#include "skeleton.dtsi"
Shawn Guoe1641532013-02-20 10:32:52 +080014#include "imx51-pinfunc.h"
Lucas Stachff65d4c2013-11-14 11:18:59 +010015#include <dt-bindings/clock/imx5-clock.h>
Alexander Shiyanbdb3eec2013-11-19 15:47:27 +040016#include <dt-bindings/gpio/gpio.h>
Alexander Shiyan72d86d22014-01-11 10:54:19 +040017#include <dt-bindings/input/input.h>
18#include <dt-bindings/interrupt-controller/irq.h>
Shawn Guo9daaf312011-10-17 08:42:17 +080019
20/ {
21 aliases {
Marek Vasut22970072014-02-28 12:58:41 +010022 ethernet0 = &fec;
Shawn Guo5230f8f2012-08-05 14:01:28 +080023 gpio0 = &gpio1;
24 gpio1 = &gpio2;
25 gpio2 = &gpio3;
26 gpio3 = &gpio4;
Sascha Hauere3b73c62013-06-25 15:51:55 +020027 i2c0 = &i2c1;
28 i2c1 = &i2c2;
Sascha Hauerf742c222014-01-16 13:44:21 +010029 mmc0 = &esdhc1;
30 mmc1 = &esdhc2;
31 mmc2 = &esdhc3;
32 mmc3 = &esdhc4;
Sascha Hauere3b73c62013-06-25 15:51:55 +020033 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 spi0 = &ecspi1;
37 spi1 = &ecspi2;
38 spi2 = &cspi;
Shawn Guo9daaf312011-10-17 08:42:17 +080039 };
40
41 tzic: tz-interrupt-controller@e0000000 {
42 compatible = "fsl,imx51-tzic", "fsl,tzic";
43 interrupt-controller;
44 #interrupt-cells = <1>;
45 reg = <0xe0000000 0x4000>;
46 };
47
48 clocks {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ckil {
53 compatible = "fsl,imx-ckil", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +080054 #clock-cells = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +080055 clock-frequency = <32768>;
56 };
57
58 ckih1 {
59 compatible = "fsl,imx-ckih1", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +080060 #clock-cells = <0>;
Alexander Shiyan677e28b2013-07-27 11:19:45 +040061 clock-frequency = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +080062 };
63
64 ckih2 {
65 compatible = "fsl,imx-ckih2", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +080066 #clock-cells = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +080067 clock-frequency = <0>;
68 };
69
70 osc {
71 compatible = "fsl,imx-osc", "fixed-clock";
Shawn Guo4b2b4042014-04-11 09:56:46 +080072 #clock-cells = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +080073 clock-frequency = <24000000>;
74 };
75 };
76
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020077 cpus {
78 #address-cells = <1>;
79 #size-cells = <0>;
Alexander Shiyan6acde882013-11-07 12:45:05 +040080 cpu: cpu@0 {
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020081 device_type = "cpu";
82 compatible = "arm,cortex-a8";
83 reg = <0>;
Alexander Shiyan6acde882013-11-07 12:45:05 +040084 clock-latency = <62500>;
Lucas Stachff65d4c2013-11-14 11:18:59 +010085 clocks = <&clks IMX5_CLK_CPU_PODF>;
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020086 clock-names = "cpu";
87 operating-points = <
Alexander Shiyan6acde882013-11-07 12:45:05 +040088 166000 1000000
89 600000 1050000
90 800000 1100000
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020091 >;
Alexander Shiyan6acde882013-11-07 12:45:05 +040092 voltage-tolerance = <5>;
Markus Pargmann6f9d62d2013-04-07 21:56:45 +020093 };
94 };
95
Alexander Shiyan4e942302013-11-19 15:47:26 +040096 usbphy {
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "simple-bus";
100
101 usbphy0: usbphy@0 {
102 compatible = "usb-nop-xceiv";
103 reg = <0>;
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
105 clock-names = "main_clk";
Sascha Hauerb5af6b12012-11-12 12:56:00 +0100106 };
107 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800108
Philipp Zabelde10e042014-03-05 10:20:59 +0100109 display-subsystem {
110 compatible = "fsl,imx-display-subsystem";
111 ports = <&ipu_di0>, <&ipu_di1>;
112 };
113
Shawn Guo9daaf312011-10-17 08:42:17 +0800114 soc {
115 #address-cells = <1>;
116 #size-cells = <1>;
117 compatible = "simple-bus";
118 interrupt-parent = <&tzic>;
119 ranges;
120
Alexander Shiyanda38ea32013-08-21 11:28:24 +0400121 iram: iram@1ffe0000 {
122 compatible = "mmio-sram";
123 reg = <0x1ffe0000 0x20000>;
124 };
125
Shawn Guo9daaf312011-10-17 08:42:17 +0800126 ipu: ipu@40000000 {
Philipp Zabelde10e042014-03-05 10:20:59 +0100127 #address-cells = <1>;
128 #size-cells = <0>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800129 compatible = "fsl,imx51-ipu";
130 reg = <0x40000000 0x20000000>;
131 interrupts = <11 10>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800135 clock-names = "bus", "di0", "di1";
136 resets = <&src 2>;
Philipp Zabelde10e042014-03-05 10:20:59 +0100137
138 ipu_di0: port@2 {
139 reg = <2>;
140
141 ipu_di0_disp0: endpoint {
142 };
143 };
144
145 ipu_di1: port@3 {
146 reg = <3>;
147
148 ipu_di1_disp1: endpoint {
149 };
150 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800151 };
152
153 aips@70000000 { /* AIPS1 */
154 compatible = "fsl,aips-bus", "simple-bus";
155 #address-cells = <1>;
156 #size-cells = <1>;
157 reg = <0x70000000 0x10000000>;
158 ranges;
159
160 spba@70000000 {
161 compatible = "fsl,spba-bus", "simple-bus";
162 #address-cells = <1>;
163 #size-cells = <1>;
164 reg = <0x70000000 0x40000>;
165 ranges;
166
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100167 esdhc1: esdhc@70004000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800168 compatible = "fsl,imx51-esdhc";
169 reg = <0x70004000 0x4000>;
170 interrupts = <1>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
172 <&clks IMX5_CLK_DUMMY>,
173 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200174 clock-names = "ipg", "ahb", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800175 status = "disabled";
176 };
177
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100178 esdhc2: esdhc@70008000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800179 compatible = "fsl,imx51-esdhc";
180 reg = <0x70008000 0x4000>;
181 interrupts = <2>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
183 <&clks IMX5_CLK_DUMMY>,
184 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200185 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200186 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800187 status = "disabled";
188 };
189
Shawn Guo0c456cf2012-04-02 14:39:26 +0800190 uart3: serial@7000c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800191 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
192 reg = <0x7000c000 0x4000>;
193 interrupts = <33>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100194 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
195 <&clks IMX5_CLK_UART3_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200196 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800197 status = "disabled";
198 };
199
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100200 ecspi1: ecspi@70010000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800201 #address-cells = <1>;
202 #size-cells = <0>;
203 compatible = "fsl,imx51-ecspi";
204 reg = <0x70010000 0x4000>;
205 interrupts = <36>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100206 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
207 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200208 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800209 status = "disabled";
210 };
211
Shawn Guoa15d9f82012-05-11 13:08:46 +0800212 ssi2: ssi@70014000 {
Alexander Shiyan6ff7f512014-08-19 20:00:09 +0400213 #sound-dai-cells = <0>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800214 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
215 reg = <0x70014000 0x4000>;
216 interrupts = <30>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800218 dmas = <&sdma 24 1 0>,
219 <&sdma 25 1 0>;
220 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800221 fsl,fifo-depth = <15>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800222 status = "disabled";
223 };
224
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100225 esdhc3: esdhc@70020000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800226 compatible = "fsl,imx51-esdhc";
227 reg = <0x70020000 0x4000>;
228 interrupts = <3>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100229 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
230 <&clks IMX5_CLK_DUMMY>,
231 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200232 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200233 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800234 status = "disabled";
235 };
236
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100237 esdhc4: esdhc@70024000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800238 compatible = "fsl,imx51-esdhc";
239 reg = <0x70024000 0x4000>;
240 interrupts = <4>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100241 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
242 <&clks IMX5_CLK_DUMMY>,
243 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200244 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200245 bus-width = <4>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800246 status = "disabled";
247 };
248 };
249
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100250 usbotg: usb@73f80000 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200251 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
252 reg = <0x73f80000 0x0200>;
253 interrupts = <18>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100254 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200255 fsl,usbmisc = <&usbmisc 0>;
Michael Grzeschika79025c2013-04-11 12:13:16 +0200256 fsl,usbphy = <&usbphy0>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200257 status = "disabled";
258 };
259
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100260 usbh1: usb@73f80200 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200261 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
262 reg = <0x73f80200 0x0200>;
263 interrupts = <14>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100264 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200265 fsl,usbmisc = <&usbmisc 1>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200266 status = "disabled";
267 };
268
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100269 usbh2: usb@73f80400 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200270 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
271 reg = <0x73f80400 0x0200>;
272 interrupts = <16>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100273 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200274 fsl,usbmisc = <&usbmisc 2>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200275 status = "disabled";
276 };
277
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100278 usbh3: usb@73f80600 {
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200279 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
280 reg = <0x73f80600 0x0200>;
281 interrupts = <17>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100282 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200283 fsl,usbmisc = <&usbmisc 3>;
Michael Grzeschik212d0b82012-08-23 12:35:57 +0200284 status = "disabled";
285 };
286
Michael Grzeschika5735022013-04-11 12:13:14 +0200287 usbmisc: usbmisc@73f80800 {
288 #index-cells = <1>;
289 compatible = "fsl,imx51-usbmisc";
290 reg = <0x73f80800 0x200>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100291 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
Michael Grzeschika5735022013-04-11 12:13:14 +0200292 };
293
Richard Zhao4d191862011-12-14 09:26:44 +0800294 gpio1: gpio@73f84000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200295 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800296 reg = <0x73f84000 0x4000>;
297 interrupts = <50 51>;
298 gpio-controller;
299 #gpio-cells = <2>;
300 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800301 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800302 };
303
Richard Zhao4d191862011-12-14 09:26:44 +0800304 gpio2: gpio@73f88000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200305 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800306 reg = <0x73f88000 0x4000>;
307 interrupts = <52 53>;
308 gpio-controller;
309 #gpio-cells = <2>;
310 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800311 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800312 };
313
Richard Zhao4d191862011-12-14 09:26:44 +0800314 gpio3: gpio@73f8c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200315 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800316 reg = <0x73f8c000 0x4000>;
317 interrupts = <54 55>;
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800321 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800322 };
323
Richard Zhao4d191862011-12-14 09:26:44 +0800324 gpio4: gpio@73f90000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200325 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
Shawn Guo9daaf312011-10-17 08:42:17 +0800326 reg = <0x73f90000 0x4000>;
327 interrupts = <56 57>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800331 #interrupt-cells = <2>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800332 };
333
Liu Ying60125552013-01-03 20:37:33 +0800334 kpp: kpp@73f94000 {
335 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
336 reg = <0x73f94000 0x4000>;
337 interrupts = <60>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100338 clocks = <&clks IMX5_CLK_DUMMY>;
Liu Ying60125552013-01-03 20:37:33 +0800339 status = "disabled";
340 };
341
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100342 wdog1: wdog@73f98000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800343 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
344 reg = <0x73f98000 0x4000>;
345 interrupts = <58>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100346 clocks = <&clks IMX5_CLK_DUMMY>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800347 };
348
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100349 wdog2: wdog@73f9c000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800350 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
351 reg = <0x73f9c000 0x4000>;
352 interrupts = <59>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100353 clocks = <&clks IMX5_CLK_DUMMY>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800354 status = "disabled";
355 };
356
Sascha Hauered73c632013-03-14 13:08:59 +0100357 gpt: timer@73fa0000 {
358 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
359 reg = <0x73fa0000 0x4000>;
360 interrupts = <39>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100361 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
362 <&clks IMX5_CLK_GPT_HF_GATE>;
Sascha Hauered73c632013-03-14 13:08:59 +0100363 clock-names = "ipg", "per";
364 };
365
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100366 iomuxc: iomuxc@73fa8000 {
Shawn Guob72cf102012-08-13 19:45:19 +0800367 compatible = "fsl,imx51-iomuxc";
368 reg = <0x73fa8000 0x4000>;
Shawn Guob72cf102012-08-13 19:45:19 +0800369 };
370
Sascha Hauer82a618d2012-11-19 00:57:08 +0100371 pwm1: pwm@73fb4000 {
372 #pwm-cells = <2>;
373 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
374 reg = <0x73fb4000 0x4000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100375 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
376 <&clks IMX5_CLK_PWM1_HF_GATE>;
Sascha Hauer82a618d2012-11-19 00:57:08 +0100377 clock-names = "ipg", "per";
378 interrupts = <61>;
379 };
380
381 pwm2: pwm@73fb8000 {
382 #pwm-cells = <2>;
383 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
384 reg = <0x73fb8000 0x4000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100385 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
386 <&clks IMX5_CLK_PWM2_HF_GATE>;
Sascha Hauer82a618d2012-11-19 00:57:08 +0100387 clock-names = "ipg", "per";
388 interrupts = <94>;
389 };
390
Shawn Guo0c456cf2012-04-02 14:39:26 +0800391 uart1: serial@73fbc000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800392 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
393 reg = <0x73fbc000 0x4000>;
394 interrupts = <31>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100395 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
396 <&clks IMX5_CLK_UART1_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200397 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800398 status = "disabled";
399 };
400
Shawn Guo0c456cf2012-04-02 14:39:26 +0800401 uart2: serial@73fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800402 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
403 reg = <0x73fc0000 0x4000>;
404 interrupts = <32>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100405 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
406 <&clks IMX5_CLK_UART2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200407 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800408 status = "disabled";
409 };
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200410
Philipp Zabel8d84c372013-03-28 17:35:23 +0100411 src: src@73fd0000 {
412 compatible = "fsl,imx51-src";
413 reg = <0x73fd0000 0x4000>;
414 #reset-cells = <1>;
415 };
416
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200417 clks: ccm@73fd4000{
418 compatible = "fsl,imx51-ccm";
419 reg = <0x73fd4000 0x4000>;
420 interrupts = <0 71 0x04 0 72 0x04>;
421 #clock-cells = <1>;
422 };
Shawn Guo9daaf312011-10-17 08:42:17 +0800423 };
424
425 aips@80000000 { /* AIPS2 */
426 compatible = "fsl,aips-bus", "simple-bus";
427 #address-cells = <1>;
428 #size-cells = <1>;
429 reg = <0x80000000 0x10000000>;
430 ranges;
431
Sascha Hauer6510ea252013-06-25 15:51:51 +0200432 iim: iim@83f98000 {
433 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
434 reg = <0x83f98000 0x4000>;
435 interrupts = <69>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100436 clocks = <&clks IMX5_CLK_IIM_GATE>;
Sascha Hauer6510ea252013-06-25 15:51:51 +0200437 };
438
Alexander Shiyanad15f082013-08-21 11:28:25 +0400439 owire: owire@83fa4000 {
440 compatible = "fsl,imx51-owire", "fsl,imx21-owire";
441 reg = <0x83fa4000 0x4000>;
442 interrupts = <88>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100443 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
Alexander Shiyanad15f082013-08-21 11:28:25 +0400444 status = "disabled";
445 };
446
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100447 ecspi2: ecspi@83fac000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800448 #address-cells = <1>;
449 #size-cells = <0>;
450 compatible = "fsl,imx51-ecspi";
451 reg = <0x83fac000 0x4000>;
452 interrupts = <37>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100453 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
454 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200455 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800456 status = "disabled";
457 };
458
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100459 sdma: sdma@83fb0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800460 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
461 reg = <0x83fb0000 0x4000>;
462 interrupts = <6>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100463 clocks = <&clks IMX5_CLK_SDMA_GATE>,
464 <&clks IMX5_CLK_SDMA_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200465 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800466 #dma-cells = <3>;
Fabio Estevam7e4f0362012-08-08 11:28:07 -0300467 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
Shawn Guo9daaf312011-10-17 08:42:17 +0800468 };
469
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100470 cspi: cspi@83fc0000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800471 #address-cells = <1>;
472 #size-cells = <0>;
473 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
474 reg = <0x83fc0000 0x4000>;
475 interrupts = <38>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100476 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
477 <&clks IMX5_CLK_CSPI_IPG_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200478 clock-names = "ipg", "per";
Shawn Guo9daaf312011-10-17 08:42:17 +0800479 status = "disabled";
480 };
481
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100482 i2c2: i2c@83fc4000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800483 #address-cells = <1>;
484 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800485 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800486 reg = <0x83fc4000 0x4000>;
487 interrupts = <63>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100488 clocks = <&clks IMX5_CLK_I2C2_GATE>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800489 status = "disabled";
490 };
491
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100492 i2c1: i2c@83fc8000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800493 #address-cells = <1>;
494 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800495 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
Shawn Guo9daaf312011-10-17 08:42:17 +0800496 reg = <0x83fc8000 0x4000>;
497 interrupts = <62>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100498 clocks = <&clks IMX5_CLK_I2C1_GATE>;
Shawn Guo9daaf312011-10-17 08:42:17 +0800499 status = "disabled";
500 };
501
Shawn Guoa15d9f82012-05-11 13:08:46 +0800502 ssi1: ssi@83fcc000 {
Alexander Shiyan6ff7f512014-08-19 20:00:09 +0400503 #sound-dai-cells = <0>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800504 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
505 reg = <0x83fcc000 0x4000>;
506 interrupts = <29>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100507 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800508 dmas = <&sdma 28 0 0>,
509 <&sdma 29 0 0>;
510 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800511 fsl,fifo-depth = <15>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800512 status = "disabled";
513 };
514
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100515 audmux: audmux@83fd0000 {
Shawn Guoa15d9f82012-05-11 13:08:46 +0800516 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
517 reg = <0x83fd0000 0x4000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100518 clocks = <&clks IMX5_CLK_DUMMY>;
Alexander Shiyane030df92013-11-07 12:45:06 +0400519 clock-names = "audmux";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800520 status = "disabled";
521 };
522
Alexander Shiyanedd05282013-07-13 08:30:57 +0400523 weim: weim@83fda000 {
524 #address-cells = <2>;
525 #size-cells = <1>;
526 compatible = "fsl,imx51-weim";
527 reg = <0x83fda000 0x1000>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100528 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
Alexander Shiyanedd05282013-07-13 08:30:57 +0400529 ranges = <
530 0 0 0xb0000000 0x08000000
531 1 0 0xb8000000 0x08000000
532 2 0 0xc0000000 0x08000000
533 3 0 0xc8000000 0x04000000
534 4 0 0xcc000000 0x02000000
535 5 0 0xce000000 0x02000000
536 >;
537 status = "disabled";
538 };
539
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100540 nfc: nand@83fdb000 {
Alexander Shiyanf0e3f892014-04-16 11:24:50 +0400541 #address-cells = <1>;
542 #size-cells = <1>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200543 compatible = "fsl,imx51-nand";
544 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
545 interrupts = <8>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100546 clocks = <&clks IMX5_CLK_NFC_GATE>;
Sascha Hauer75453a02012-06-06 12:33:16 +0200547 status = "disabled";
548 };
549
Sascha Hauer718a35002013-04-04 11:25:09 +0200550 pata: pata@83fe0000 {
551 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
552 reg = <0x83fe0000 0x4000>;
553 interrupts = <70>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100554 clocks = <&clks IMX5_CLK_PATA_GATE>;
Sascha Hauer718a35002013-04-04 11:25:09 +0200555 status = "disabled";
556 };
557
Shawn Guoa15d9f82012-05-11 13:08:46 +0800558 ssi3: ssi@83fe8000 {
Alexander Shiyan6ff7f512014-08-19 20:00:09 +0400559 #sound-dai-cells = <0>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800560 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
561 reg = <0x83fe8000 0x4000>;
562 interrupts = <96>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100563 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
Shawn Guo5da826a2013-07-17 13:50:54 +0800564 dmas = <&sdma 46 0 0>,
565 <&sdma 47 0 0>;
566 dma-names = "rx", "tx";
Shawn Guoa15d9f82012-05-11 13:08:46 +0800567 fsl,fifo-depth = <15>;
Shawn Guoa15d9f82012-05-11 13:08:46 +0800568 status = "disabled";
569 };
570
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100571 fec: ethernet@83fec000 {
Shawn Guo9daaf312011-10-17 08:42:17 +0800572 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
573 reg = <0x83fec000 0x4000>;
574 interrupts = <87>;
Lucas Stachff65d4c2013-11-14 11:18:59 +0100575 clocks = <&clks IMX5_CLK_FEC_GATE>,
576 <&clks IMX5_CLK_FEC_GATE>,
577 <&clks IMX5_CLK_FEC_GATE>;
Fabio Estevamf40f38d2012-11-21 13:43:05 -0200578 clock-names = "ipg", "ahb", "ptp";
Shawn Guo9daaf312011-10-17 08:42:17 +0800579 status = "disabled";
580 };
581 };
582 };
583};