blob: d9ffe1f56e8fc2aca4acc845b1e470ceb9642203 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <drm/drmP.h>
34#include "radeon_drm.h"
35#include "radeon.h"
36
Jerome Glisse771fe6b2009-06-05 14:42:42 +020037
38int radeon_ttm_init(struct radeon_device *rdev);
39void radeon_ttm_fini(struct radeon_device *rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +010040static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020041
42/*
43 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
44 * function are calling it.
45 */
46
Jerome Glisse4c788672009-11-20 14:29:23 +010047static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020048{
Jerome Glisse4c788672009-11-20 14:29:23 +010049 struct radeon_bo *bo;
50
51 bo = container_of(tbo, struct radeon_bo, tbo);
52 mutex_lock(&bo->rdev->gem.mutex);
53 list_del_init(&bo->list);
54 mutex_unlock(&bo->rdev->gem.mutex);
55 radeon_bo_clear_surface_reg(bo);
56 kfree(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020057}
58
Jerome Glissed03d8582009-12-14 21:02:09 +010059bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
60{
61 if (bo->destroy == &radeon_ttm_bo_destroy)
62 return true;
63 return false;
64}
65
Jerome Glisse312ea8d2009-12-07 15:52:58 +010066void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
67{
68 u32 c = 0;
69
70 rbo->placement.fpfn = 0;
71 rbo->placement.lpfn = 0;
72 rbo->placement.placement = rbo->placements;
73 rbo->placement.busy_placement = rbo->placements;
74 if (domain & RADEON_GEM_DOMAIN_VRAM)
75 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
76 TTM_PL_FLAG_VRAM;
77 if (domain & RADEON_GEM_DOMAIN_GTT)
78 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
79 if (domain & RADEON_GEM_DOMAIN_CPU)
80 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
Jerome Glisse9fb03e62009-12-11 15:13:22 +010081 if (!c)
82 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
Jerome Glisse312ea8d2009-12-07 15:52:58 +010083 rbo->placement.num_placement = c;
84 rbo->placement.num_busy_placement = c;
85}
86
Jerome Glisse4c788672009-11-20 14:29:23 +010087int radeon_bo_create(struct radeon_device *rdev, struct drm_gem_object *gobj,
88 unsigned long size, bool kernel, u32 domain,
89 struct radeon_bo **bo_ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090{
Jerome Glisse4c788672009-11-20 14:29:23 +010091 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020092 enum ttm_bo_type type;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020093 int r;
94
95 if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
96 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
97 }
98 if (kernel) {
99 type = ttm_bo_type_kernel;
100 } else {
101 type = ttm_bo_type_device;
102 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100103 *bo_ptr = NULL;
104 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
105 if (bo == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200106 return -ENOMEM;
Jerome Glisse4c788672009-11-20 14:29:23 +0100107 bo->rdev = rdev;
108 bo->gobj = gobj;
109 bo->surface_reg = -1;
110 INIT_LIST_HEAD(&bo->list);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200111
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100112 radeon_ttm_placement_from_domain(bo, domain);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100113 /* Kernel allocation are uninterruptible */
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100114 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
115 &bo->placement, 0, 0, !kernel, NULL, size,
116 &radeon_ttm_bo_destroy);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200117 if (unlikely(r != 0)) {
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100118 if (r != -ERESTARTSYS)
119 dev_err(rdev->dev,
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100120 "object_init failed for (%lu, 0x%08X)\n",
121 size, domain);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200122 return r;
123 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100124 *bo_ptr = bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200125 if (gobj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100126 mutex_lock(&bo->rdev->gem.mutex);
127 list_add_tail(&bo->list, &rdev->gem.objects);
128 mutex_unlock(&bo->rdev->gem.mutex);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200129 }
130 return 0;
131}
132
Jerome Glisse4c788672009-11-20 14:29:23 +0100133int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200134{
Jerome Glisse4c788672009-11-20 14:29:23 +0100135 bool is_iomem;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200136 int r;
137
Jerome Glisse4c788672009-11-20 14:29:23 +0100138 if (bo->kptr) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200139 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100140 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200141 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200142 return 0;
143 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100144 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200145 if (r) {
146 return r;
147 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100148 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200149 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100150 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200151 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100152 radeon_bo_check_tiling(bo, 0, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200153 return 0;
154}
155
Jerome Glisse4c788672009-11-20 14:29:23 +0100156void radeon_bo_kunmap(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200157{
Jerome Glisse4c788672009-11-20 14:29:23 +0100158 if (bo->kptr == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200159 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100160 bo->kptr = NULL;
161 radeon_bo_check_tiling(bo, 0, 0);
162 ttm_bo_kunmap(&bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200163}
164
Jerome Glisse4c788672009-11-20 14:29:23 +0100165void radeon_bo_unref(struct radeon_bo **bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200166{
Jerome Glisse4c788672009-11-20 14:29:23 +0100167 struct ttm_buffer_object *tbo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200168
Jerome Glisse4c788672009-11-20 14:29:23 +0100169 if ((*bo) == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200170 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100171 tbo = &((*bo)->tbo);
172 ttm_bo_unref(&tbo);
173 if (tbo == NULL)
174 *bo = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200175}
176
Jerome Glisse4c788672009-11-20 14:29:23 +0100177int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200178{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100179 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200180
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100181 radeon_ttm_placement_from_domain(bo, domain);
Jerome Glisse4c788672009-11-20 14:29:23 +0100182 if (bo->pin_count) {
183 bo->pin_count++;
184 if (gpu_addr)
185 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200186 return 0;
187 }
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100188 radeon_ttm_placement_from_domain(bo, domain);
189 for (i = 0; i < bo->placement.num_placement; i++)
190 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100191 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
Jerome Glisse4c788672009-11-20 14:29:23 +0100192 if (likely(r == 0)) {
193 bo->pin_count = 1;
194 if (gpu_addr != NULL)
195 *gpu_addr = radeon_bo_gpu_offset(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200196 }
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100197 if (unlikely(r != 0))
Jerome Glisse4c788672009-11-20 14:29:23 +0100198 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200199 return r;
200}
201
Jerome Glisse4c788672009-11-20 14:29:23 +0100202int radeon_bo_unpin(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200203{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100204 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200205
Jerome Glisse4c788672009-11-20 14:29:23 +0100206 if (!bo->pin_count) {
207 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
208 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200209 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100210 bo->pin_count--;
211 if (bo->pin_count)
212 return 0;
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100213 for (i = 0; i < bo->placement.num_placement; i++)
214 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100215 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100216 if (unlikely(r != 0))
Jerome Glisse4c788672009-11-20 14:29:23 +0100217 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100218 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200219}
220
Jerome Glisse4c788672009-11-20 14:29:23 +0100221int radeon_bo_evict_vram(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200222{
223 if (rdev->flags & RADEON_IS_IGP) {
224 /* Useless to evict on IGP chips */
225 return 0;
226 }
227 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
228}
229
Jerome Glisse4c788672009-11-20 14:29:23 +0100230void radeon_bo_force_delete(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200231{
Jerome Glisse4c788672009-11-20 14:29:23 +0100232 struct radeon_bo *bo, *n;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200233 struct drm_gem_object *gobj;
234
235 if (list_empty(&rdev->gem.objects)) {
236 return;
237 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100238 dev_err(rdev->dev, "Userspace still has active objects !\n");
239 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200240 mutex_lock(&rdev->ddev->struct_mutex);
Jerome Glisse4c788672009-11-20 14:29:23 +0100241 gobj = bo->gobj;
242 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
243 gobj, bo, (unsigned long)gobj->size,
244 *((unsigned long *)&gobj->refcount));
245 mutex_lock(&bo->rdev->gem.mutex);
246 list_del_init(&bo->list);
247 mutex_unlock(&bo->rdev->gem.mutex);
248 radeon_bo_unref(&bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200249 gobj->driver_private = NULL;
250 drm_gem_object_unreference(gobj);
251 mutex_unlock(&rdev->ddev->struct_mutex);
252 }
253}
254
Jerome Glisse4c788672009-11-20 14:29:23 +0100255int radeon_bo_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200256{
Jerome Glissea4d68272009-09-11 13:00:43 +0200257 /* Add an MTRR for the VRAM */
258 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
259 MTRR_TYPE_WRCOMB, 1);
260 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
261 rdev->mc.mc_vram_size >> 20,
262 (unsigned long long)rdev->mc.aper_size >> 20);
263 DRM_INFO("RAM width %dbits %cDR\n",
264 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200265 return radeon_ttm_init(rdev);
266}
267
Jerome Glisse4c788672009-11-20 14:29:23 +0100268void radeon_bo_fini(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200269{
270 radeon_ttm_fini(rdev);
271}
272
Jerome Glisse4c788672009-11-20 14:29:23 +0100273void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
274 struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200275{
276 if (lobj->wdomain) {
277 list_add(&lobj->list, head);
278 } else {
279 list_add_tail(&lobj->list, head);
280 }
281}
282
Jerome Glisse4c788672009-11-20 14:29:23 +0100283int radeon_bo_list_reserve(struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200284{
Jerome Glisse4c788672009-11-20 14:29:23 +0100285 struct radeon_bo_list *lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200286 int r;
287
Dave Airlie9d8401f2009-10-08 09:28:19 +1000288 list_for_each_entry(lobj, head, list){
Jerome Glisse4c788672009-11-20 14:29:23 +0100289 r = radeon_bo_reserve(lobj->bo, false);
290 if (unlikely(r != 0))
291 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200292 }
293 return 0;
294}
295
Jerome Glisse4c788672009-11-20 14:29:23 +0100296void radeon_bo_list_unreserve(struct list_head *head)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200297{
Jerome Glisse4c788672009-11-20 14:29:23 +0100298 struct radeon_bo_list *lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200299
Dave Airlie9d8401f2009-10-08 09:28:19 +1000300 list_for_each_entry(lobj, head, list) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100301 /* only unreserve object we successfully reserved */
302 if (radeon_bo_is_reserved(lobj->bo))
303 radeon_bo_unreserve(lobj->bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200304 }
305}
306
Jerome Glisse4c788672009-11-20 14:29:23 +0100307int radeon_bo_list_validate(struct list_head *head, void *fence)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200308{
Jerome Glisse4c788672009-11-20 14:29:23 +0100309 struct radeon_bo_list *lobj;
310 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200311 struct radeon_fence *old_fence = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200312 int r;
313
Jerome Glisse4c788672009-11-20 14:29:23 +0100314 r = radeon_bo_list_reserve(head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200315 if (unlikely(r != 0)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200316 return r;
317 }
Dave Airlie9d8401f2009-10-08 09:28:19 +1000318 list_for_each_entry(lobj, head, list) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100319 bo = lobj->bo;
320 if (!bo->pin_count) {
Michel Dänzer664f8652009-07-28 12:30:57 +0200321 if (lobj->wdomain) {
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100322 radeon_ttm_placement_from_domain(bo,
323 lobj->wdomain);
Michel Dänzer664f8652009-07-28 12:30:57 +0200324 } else {
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100325 radeon_ttm_placement_from_domain(bo,
326 lobj->rdomain);
Michel Dänzer664f8652009-07-28 12:30:57 +0200327 }
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100328 r = ttm_bo_validate(&bo->tbo, &bo->placement,
Jerome Glisse4c788672009-11-20 14:29:23 +0100329 true, false);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100330 if (unlikely(r))
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200331 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200332 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100333 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
334 lobj->tiling_flags = bo->tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200335 if (fence) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100336 old_fence = (struct radeon_fence *)bo->tbo.sync_obj;
337 bo->tbo.sync_obj = radeon_fence_ref(fence);
338 bo->tbo.sync_obj_arg = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200339 }
340 if (old_fence) {
341 radeon_fence_unref(&old_fence);
342 }
343 }
344 return 0;
345}
346
Jerome Glisse4c788672009-11-20 14:29:23 +0100347void radeon_bo_list_unvalidate(struct list_head *head, void *fence)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200348{
Jerome Glisse4c788672009-11-20 14:29:23 +0100349 struct radeon_bo_list *lobj;
350 struct radeon_fence *old_fence;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200351
Jerome Glisse4c788672009-11-20 14:29:23 +0100352 if (fence)
353 list_for_each_entry(lobj, head, list) {
354 old_fence = to_radeon_fence(lobj->bo->tbo.sync_obj);
355 if (old_fence == fence) {
356 lobj->bo->tbo.sync_obj = NULL;
357 radeon_fence_unref(&old_fence);
358 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200359 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100360 radeon_bo_list_unreserve(head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200361}
362
Jerome Glisse4c788672009-11-20 14:29:23 +0100363int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200364 struct vm_area_struct *vma)
365{
Jerome Glisse4c788672009-11-20 14:29:23 +0100366 return ttm_fbdev_mmap(vma, &bo->tbo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200367}
368
Dave Airlie550e2d92009-12-09 14:15:38 +1000369int radeon_bo_get_surface_reg(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200370{
Jerome Glisse4c788672009-11-20 14:29:23 +0100371 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000372 struct radeon_surface_reg *reg;
Jerome Glisse4c788672009-11-20 14:29:23 +0100373 struct radeon_bo *old_object;
Dave Airliee024e112009-06-24 09:48:08 +1000374 int steal;
375 int i;
376
Jerome Glisse4c788672009-11-20 14:29:23 +0100377 BUG_ON(!atomic_read(&bo->tbo.reserved));
378
379 if (!bo->tiling_flags)
Dave Airliee024e112009-06-24 09:48:08 +1000380 return 0;
381
Jerome Glisse4c788672009-11-20 14:29:23 +0100382 if (bo->surface_reg >= 0) {
383 reg = &rdev->surface_regs[bo->surface_reg];
384 i = bo->surface_reg;
Dave Airliee024e112009-06-24 09:48:08 +1000385 goto out;
386 }
387
388 steal = -1;
389 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
390
391 reg = &rdev->surface_regs[i];
Jerome Glisse4c788672009-11-20 14:29:23 +0100392 if (!reg->bo)
Dave Airliee024e112009-06-24 09:48:08 +1000393 break;
394
Jerome Glisse4c788672009-11-20 14:29:23 +0100395 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000396 if (old_object->pin_count == 0)
397 steal = i;
398 }
399
400 /* if we are all out */
401 if (i == RADEON_GEM_MAX_SURFACES) {
402 if (steal == -1)
403 return -ENOMEM;
404 /* find someone with a surface reg and nuke their BO */
405 reg = &rdev->surface_regs[steal];
Jerome Glisse4c788672009-11-20 14:29:23 +0100406 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000407 /* blow away the mapping */
408 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
Jerome Glisse4c788672009-11-20 14:29:23 +0100409 ttm_bo_unmap_virtual(&old_object->tbo);
Dave Airliee024e112009-06-24 09:48:08 +1000410 old_object->surface_reg = -1;
411 i = steal;
412 }
413
Jerome Glisse4c788672009-11-20 14:29:23 +0100414 bo->surface_reg = i;
415 reg->bo = bo;
Dave Airliee024e112009-06-24 09:48:08 +1000416
417out:
Jerome Glisse4c788672009-11-20 14:29:23 +0100418 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
419 bo->tbo.mem.mm_node->start << PAGE_SHIFT,
420 bo->tbo.num_pages << PAGE_SHIFT);
Dave Airliee024e112009-06-24 09:48:08 +1000421 return 0;
422}
423
Jerome Glisse4c788672009-11-20 14:29:23 +0100424static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
Dave Airliee024e112009-06-24 09:48:08 +1000425{
Jerome Glisse4c788672009-11-20 14:29:23 +0100426 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000427 struct radeon_surface_reg *reg;
428
Jerome Glisse4c788672009-11-20 14:29:23 +0100429 if (bo->surface_reg == -1)
Dave Airliee024e112009-06-24 09:48:08 +1000430 return;
431
Jerome Glisse4c788672009-11-20 14:29:23 +0100432 reg = &rdev->surface_regs[bo->surface_reg];
433 radeon_clear_surface_reg(rdev, bo->surface_reg);
Dave Airliee024e112009-06-24 09:48:08 +1000434
Jerome Glisse4c788672009-11-20 14:29:23 +0100435 reg->bo = NULL;
436 bo->surface_reg = -1;
Dave Airliee024e112009-06-24 09:48:08 +1000437}
438
Jerome Glisse4c788672009-11-20 14:29:23 +0100439int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
440 uint32_t tiling_flags, uint32_t pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000441{
Jerome Glisse4c788672009-11-20 14:29:23 +0100442 int r;
443
444 r = radeon_bo_reserve(bo, false);
445 if (unlikely(r != 0))
446 return r;
447 bo->tiling_flags = tiling_flags;
448 bo->pitch = pitch;
449 radeon_bo_unreserve(bo);
450 return 0;
Dave Airliee024e112009-06-24 09:48:08 +1000451}
452
Jerome Glisse4c788672009-11-20 14:29:23 +0100453void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
454 uint32_t *tiling_flags,
455 uint32_t *pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000456{
Jerome Glisse4c788672009-11-20 14:29:23 +0100457 BUG_ON(!atomic_read(&bo->tbo.reserved));
Dave Airliee024e112009-06-24 09:48:08 +1000458 if (tiling_flags)
Jerome Glisse4c788672009-11-20 14:29:23 +0100459 *tiling_flags = bo->tiling_flags;
Dave Airliee024e112009-06-24 09:48:08 +1000460 if (pitch)
Jerome Glisse4c788672009-11-20 14:29:23 +0100461 *pitch = bo->pitch;
Dave Airliee024e112009-06-24 09:48:08 +1000462}
463
Jerome Glisse4c788672009-11-20 14:29:23 +0100464int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
465 bool force_drop)
Dave Airliee024e112009-06-24 09:48:08 +1000466{
Jerome Glisse4c788672009-11-20 14:29:23 +0100467 BUG_ON(!atomic_read(&bo->tbo.reserved));
468
469 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
Dave Airliee024e112009-06-24 09:48:08 +1000470 return 0;
471
472 if (force_drop) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100473 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000474 return 0;
475 }
476
Jerome Glisse4c788672009-11-20 14:29:23 +0100477 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
Dave Airliee024e112009-06-24 09:48:08 +1000478 if (!has_moved)
479 return 0;
480
Jerome Glisse4c788672009-11-20 14:29:23 +0100481 if (bo->surface_reg >= 0)
482 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000483 return 0;
484 }
485
Jerome Glisse4c788672009-11-20 14:29:23 +0100486 if ((bo->surface_reg >= 0) && !has_moved)
Dave Airliee024e112009-06-24 09:48:08 +1000487 return 0;
488
Jerome Glisse4c788672009-11-20 14:29:23 +0100489 return radeon_bo_get_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000490}
491
492void radeon_bo_move_notify(struct ttm_buffer_object *bo,
Jerome Glissed03d8582009-12-14 21:02:09 +0100493 struct ttm_mem_reg *mem)
Dave Airliee024e112009-06-24 09:48:08 +1000494{
Jerome Glissed03d8582009-12-14 21:02:09 +0100495 struct radeon_bo *rbo;
496 if (!radeon_ttm_bo_is_radeon_bo(bo))
497 return;
498 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100499 radeon_bo_check_tiling(rbo, 0, 1);
Dave Airliee024e112009-06-24 09:48:08 +1000500}
501
502void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
503{
Jerome Glissed03d8582009-12-14 21:02:09 +0100504 struct radeon_bo *rbo;
505 if (!radeon_ttm_bo_is_radeon_bo(bo))
506 return;
507 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100508 radeon_bo_check_tiling(rbo, 0, 0);
Dave Airliee024e112009-06-24 09:48:08 +1000509}